T10/11-404r1
To:T10 Technical Committee
From:Kevin Marks
Date:May 10, 2012
Subject:T10/11-404r1–SOP:SOP – Annex B
Revision History
Revision 0 (1/08/2012) – Initial Proposal
Revision 1 (5/10/2012)
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Related Documents
SCSI over PCIe(r) architecture (SOP) (T10/ 2239-D SOPr1a)
New text to be added to SOP
Text to be deleted from SOP
Editorial text
Overview
Annex for SOP mapping to NVMe queuing specific details
Suggested Changes to SOP (All NEW Text)
Editor’s note – Need to add a reference to NVM Express as NVMe
Annex B
(Normative)
Mapping SOP over NVM Express
A.1 NVM Expressspecific SOP IU fields
A.1.1 QUEING INTERFACE SPECIFIC field
Table A.1 shows the QUEUING INTERFACE SPECIFIC field definition for a request IU (see table 19).
Byte\Bit / 7 / 6 / 5 / 4 / 3 / 2 / 1 / 00 / Reserved
...
3
Table A.1 - QUEUING INTERFACE SPECIFIC field definition for request IU
Editor Note: When NVMe groups adds support for SGL’s an SGL bit will be added to indicate the data descriptors are SGL based and not PRP and definition of the Data Buffer descriptor area.
Table A.2 shows the QUEUING INTERFACE SPECIFIC field definition for a response IU (see table 19)
Table A.2 - QUEUING INTERFACE SPECIFIC field definition for response IU
Byte\Bit / 7 / 6 / 5 / 4 / 3 / 2 / 1 / 00 / SQ IDENTIFIER / (LSB) / PHASE TAG
1 / (MSB)
2 / SQ HEAD POINTER / (LSB)
3 / (MSB)
See NVM Express for a description of the:
a)SQ IDENTIFIERfield;
b)PHASE TAG field; and
c)SQ HEAD POINTERfield.
NOTE X –NVM Express defines the SQ IDENTIFIER field as a 16 bit field, however when using this standard over NVM Express the SQ IDENTIFIER field is limited to 15 bits or 32768 Submission Queues (see NVMe), with SQ Identifier 0h being reserved for the Admin Queue.
A.1.2Data Buffer Descriptor
Table A.3 defines the contents of the Data Buffer descriptor area.
Table A.3 — Contents of the Data Buffer descriptor area
Byte\Bit / 7 / 6 / 5 / 4 / 3 / 2 / 1 / 00 / PRP1
…
7
8 / PRP2 or PRP List
…
15
The Data Buffer descriptor area contents are dependent on the amount of data to be transferred by the command and the memory page size as specified in the Memory Page Size field of the Controller Configuration register (See NVMe.) The contents of the Data Buffer descriptor area may contain:
a)a PRP1 with PRP2 reserved;
b)a PRP1 and a PRP2; or
c)a PRP1 and a PRP List.
The definition and format for the PRP1 field, PRP2 field and PRP LIST field are described in NVM Express.
A.1.3Queuing-layer specific IQ error information for NVMe
Table A.4 defines the queuing-layer-specific IQ error information for NVMe.
Table A.4 — Queuing-layer-specific IQ error information for NVMe
Byte\Bit / 7 / 6 / 5 / 4 / 3 / 2 / 1 / 00 / BAD SQ QUEUE IDENTIFIER / (LSB)
1 / (MSB)
2 / Reserved
3
4 / BAD SQ QUEUE ELEMENT INDEX / (LSB)
5 / (MSB)
6 / Reserved
7
The BAD SQ QUEUE IDENTIFIER field indicates the Submission Queue (SQ) in which the bad IU was received.
The BAD SQ QUEUE ELEMENT INDEX field indicates the element index in the Submission Queue (SQ) in which the bad IU was received.
NOTE x - The SOP target port may have consumed the elements containing the bad IU and the SOP initiatorport may have produced a new IU over those elements by the time that the IQ ERROR IU is returned in the errorqueue.
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