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Background Statement for SEMI Draft Document 5688A
NEW STANDARD: GUIDE FOR OVERLAY PERFORMANCE ASSESSMENT FOR 3DS-IC PROCESS
Notice: This background statement is not part of the balloted item. It is provided solely to assist the recipient in reaching an informed decision based on the rationale of the activity that preceded the creation of this Document.
Notice: Recipients of this Document are invited to submit, with their comments, notification of any relevant patented technology or copyrighted items of which they are aware and to provide supporting documentation. In this context, “patented technology” is defined as technology for which a patent has issued or has been applied for. In the latter case, only publicly available information on the contents of the patent application is to be provided.
Background Statement:
SEMI Draft Document 5688A was developed by the 3DS-IC Middle End Process Task Force to define generic overlay target design methodology, instrument configuration, measurement algorithm and analysis model for F2F/F2B wafer in 3D-IS process, and develop criteria for describing overlay performance in terms of translation, expansion, rotation, residue and vector plots errors.
Review and Adjudication Information
Task Force Review / Committee AdjudicationGroup: / Middle End Process Task Force / Taiwan 3DS-IC TC Chapter
Date: / TBD / Oct 6, 2015
Time & Timezone: / TBD / 14:00-16:00 Taipei Time (GMT+8)
Location: / TBD / SEMI Taiwan Office
City, State/Country: / Hsinchu, Taiwan / Hsinchu, Taiwan
Leader(s): / Yi-Sha Ku (ITRI)
Bin-Cheng Yao (ITRI)
/ Tzu-Kun Ku (ITRI)
Wendy Chen (King Yuan Electronics)
Roger Hwang (ASE)
Standards Staff: / Andy Tuan (SEMI Taiwan)
+886.3.560.1777 / / Andy Tuan (SEMI Taiwan)
+886.3.560.1777 /
This meeting’s details are subject to change, and additional review sessions may be scheduled if necessary. Contact Standards staff for confirmation.
Telephone and web information will be distributed to interested parties as the meeting date approaches. If you will not be able to attend these meetings in person but would like to participate by telephone/web, please contact Standards staff. Check www.semi.org/standards on calendar of event for the latest meeting schedule.
SEMI Draft Document 5688A
NEW STANDARD: GUIDE FOR OVERLAY PERFORMANCE ASSESSMENT FOR 3DS-IC PROCESS
1 Purpose
1.1 This Guide will assist the user in conducting the overlay performance assessment for the Face-to-Back (F2B) and Face-to-Face (F2F) wafer in 3DS-IC process. A generic overlay performance assessment specification will be addressed in order to provide criteria and common baselines of the middle-end process for related upstream and downstream manufacturers fabricating the 3DS-IC products.
2 Scope
2.1 This guide will provide a generic optical measurement methodology and linear dimensional parameters such as translation, expansion, rotation, residue errors and vector plots for overlay performance assessment in 3D-IC middle end process quality control. It includes generic overlay target design methodology, instrument configuration, theoretical model and measurement algorithm consideration for F2F and F2B wafer in 3D-IS process. It focuses on the various measurement methods available, rather than on particular instruments. This guide does not provide an exhaustive list of the state of the art of overlay methodology of 3D-IC process.
3 Limitations
3.1 This document does not specify details of overlay measurement procedures.
4 Referenced Standards and Documents
4.1 SEMI Standards and Safety Guidelines
SEMI 3D7 ─ Guide for Alignment Mark for 3DS-IC Process
SEMI P18 ─ Specification for Overlay Capabilities of Wafer Steppers
SEMI P28 ─ Specification for Overlay-Metrology Test Patterns for Integrated-Circuit Manufacture
NOTICE: Unless otherwise indicated, all documents cited shall be the latest published versions.
5 Terminology
5.1 Abbreviations and Acronyms
5.1.1 C2C — Chip to Chip
5.1.2 C2W — Chip to Wafer
5.1.3 F2B — Face to Back
5.1.4 F2F — Face to Face
5.1.5 OM — Optical Microscopy
5.1.6 W2W — Wafer to Wafer
5.2 Definitions
5.2.1 overlay — A vector quantity defined at every point on the wafer. It is the difference, , between the vector position, , of a substrate geometry, and the vector position of the corresponding point, , in an overlaying pattern, which may consist of photoresist:
5.2.2 registration — A vector quantity defined at every point on the wafer. It is the difference, , between the vector position, , of a substrate geometry, and the vector position of the corresponding point, , in a reference grid:
Note that overlay is a relative quantity, while registration is an error compared to an absolute standard .
5.2.3 offset direction — Overlay vectors should be decomposed into orthogonal components, X and Y, along the directions of the stepper stage motion, and a rotation angle q calculated by X and Y offset values. X Direction is positive to the right, Y Direction is positive to the up, Theta direction is positive counter clockwise, as indicated in the following figure.
5.2.4 Centerline — A reference line that is equidistant from opposite edges of a feature.
5.2.5 Feature — Area within a single continuous boundary that have any physical property that is distinct from the background area outside the feature.
5.2.6 Pattern — A group of features for overlay metrology
Note: Figure 1: schematic illustration for definition 5.2.1. Figure 2: schematic illustration for definition 5.2.2.
Figure 3: schematic illustration for definition 5.2.3. Figure 4: schematic illustration for definition 5.2.5/5.2.6.
Figure 1
Schematic of Overlay Vectors
Figure 2
Schematic of Registration Processes, Left: Before Photolithography, Right: After Photolithography
Figure 3
Overlay Vectors Definition
Figure 4
Features and Pattern
6 Sample and Instrumentation General Specification
6.1 Overlay pattern design guideline
a. The pattern should be able to represent in-circuit errors (e.g. box-based and frame-based marks).
b. The pattern should be robust to process circuit damage.
c. The pattern should not introduce new classes of error (e.g. large areas which will become dished during CMP operations).
d. The pattern should be practical to be printed in production conditions.
e. Different patterns structures should be printed at different layers of stacking wafer surfaces.
f. General methodology: 2-Dimensional symmetrical targets are recommended. The patterns should be symmetric with respect to vertical and horizontal centerlines (90o rotational symmetry). Space must be provided between patterned line edges to avoid optical measurement interference. The designed patterns should be large enough for easy imaging by Infrared bright-field microscopy. The specific patterns can be box-in-box, frame-in-frame, or bar-in-bar. The following figures are designed examples.
Figure 5
Examples of 90o Rotational Symmetry Pattern for Overlay Measurement
6.2 Overlay measurement position guideline
6.2.1 General guideline
a. Place the overlay pattern near device regions of interest.
b. The suggested minimum size for the overlay pattern used with infrared optical microscopy is 10 μm x 10 μm.
c. Distinct in-chip pattern — The general in-chip patterns are too small and dense to be easily measured. However, the distinct in-chip patterns sometimes can be found and selected for overlay measurement.
d. Device scribe lines (wafer level bonding)
Scribe lines are typical 100 µm wide. Special measurement patterns can be designed in this region for W2W level process.
Figure 6
Schematic of Device Scribe Lines
6.3 General instrument configuration
6.3.1 Since IR wavelengths can transmit through the silicon, infrared microscopy makes it possible to capture images through bulk silicon for 3D Interconnect metrology. The generic schematic diagram of the infrared microscopy is as shown in Figure 7.
Figure 7
Generic Infrared Microscopy Configuration
7 Overlay performance assessment guideline
7.1 measurement algorithm
7.1.1 Overlay of structures on all possible surfaces of a substrate or bonded substrates should be measured. Using different lots of bonded wafers, alignment offset and electrical test data can be used to correlate overlay offset with yield. The general measurement rules are:
a. F2F bonded wafer pairs: Single image will be taken, when depth of focus (DOF) is sufficient to include both surfaces. Multiple image techniques will be taken, when DOF is not enough (for example, multiple Z planes). Following figure is schematic diagram for F2F measurement.
Figure 8
Schematic Diagram for F2F Measurement, Left: DOF is Sufficient, Right: DOF is not Enough
b. F2B bonded wafer pairs: Multiple images will be taken, especially for top and bottom surface of the bonded wafer pairs. Two images with the same (X, Y) but separate Z location are merged for overlay measurement. Following figure is schematic diagram for F2B measurement.
Figure 9
Schematic Diagram of Images Process for F2B Bonded Wafer Pairs
c. Overlay analysis algorithms: Reliable measurement depends on line edge detection quality of the images taken. Some factors affecting the line edge detection are pattern geometry/material, bond quality, image focus, doping level, Z distance between 2 layers, etc. The general line edge measurement methods are threshold, derivative, and pattern recognition method.
7.2 Analysis model
7.3 A linear model is used to describe the interfield errors by considering the overlay error at equivalent points in each exposure field. Let (X, Y) be the coordinates of a point on the wafer corresponding to the wafer center. (The center of the wafer is the most convenient location for the origin of the coordinate system.) The overlay error in the X and Y directions, DX and DY, respectively, can be expressed as:
DX = TX + EX X - RX Y + eX (1)
DY = TY + EY Y + RY X + eY (2)
Where the parameters TX and TY represent translation errors in the X and Y directions, respectively, and indicate an overall shift of one die relative to the other. The factors EX and EY are scale errors that represent the errors made by the bonder in compensating for wafer expansion or contraction (scale errors are dimensionless and are usually expressed in parts-per-million (ppm)). The coefficients RX and RY are rotation factors. When RX =RY one die is rotated relative to the other, and this accounts for the sign convention. The rotations are usually expressed in radians, typically in units of microradians. There are also residual errors at every measured point, eX and eY, which do not conform to the model. The data was fitted to a linear model of the bonder behavior, using data from each of the measurement targets in turn. Following Figure 10 shows a typical display of the measured overlay maps and statistic results of statistical analysis of the translation/scaling/rotation errors.
Figure 10
Typical Display of the Measured Overlay Maps and Results from Linear Model Analysis
7.4 General Cautions for Applications
7.4.1 Matching error: A set of additional overlay errors not included in the overlay models are found in situations where more than one stepper is used. They refer to the degree on to which the pattern placement produced on one stepper matches that of other steppers. There can be grid and intrafield matching errors.
7.4.2 Misregistration: Misregistration of geometries on reticles results in overlay errors on wafers. This misregistration can have random components, as well as other contributions that vary systematically across the reticles.
7.4.3 Process-dependent overlay effects: The quality of the overlay is very dependent upon the accuracy of the alignment targets, which depends upon the overall process for making semiconductors, including film depositions, resist coatings, etches, and polishes. For example, sputtering geometries are usually radially symmetric, the resulting overlay errors often appear as wafer scaling errors; alignment target deformation occurs from all CMP processes which makes overlay difficult because it reduces alignment target contrast.
7.4.4 Tool induced shift (TIS) effects: TIS is a measure of the systematic error contribution to the overlay measurement resulting from the imperfection of the overlay measurement process (tool-target optical interaction). It can be described as the average of the overlay measurements performed on a given overlay mark at 0° and 180° orientation. Non-zero TIS is an indication that the metrology tool has induced a systematic discrepancy in the overlay result due to the above system imperfections. TIS is however, by definition, a correctable error. A more important metrology uncertainty contributor is TIS variability, defined as 3 times the standard deviation of the TIS measured over N sites across the wafer. TIS-variability is one of the main contributors to measurement uncertainty, as it sets a lower limit to possible TIS-correction. TIS-variability reduction usually involves the improvements of the metrology tools and methods.
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