Timing for the Address and Data Buses Is Shown Below. the Asserted Low MREQN Signal (Not

ECE4623/5623

Project

Due: 12/12/12 - 4:30pm

Prof. M.P. Tull

1. In this project we will design a simplified bus memory/peripheral controller, somewhat like an ARM asynchronous (Intel-style) 32-bit address and data buses with memory mapped IO assumed. Select a Spartan3E device. The controller is intended to control memory accesses for fast external SRAM and slower flash memories, provide partial decoding for the 4 GB address space, provide additional GPIO via added input and output data ports, and use of the Xilinx Digital Clock Manager to provide a 2x clock for use by the controller and peripheral devices. Note that, unlike Intel devices, all peripheral devices reside in the same address space as the memory (memory mapped IO).

Timing for the address and data buses is shown below. The asserted low MREQN signal (not shown) is sourced by the processor, prior to the start of the memory cycle, to indicate a memory cycle is beginning. (The MREQN can provide general enabling of the bus controller circuit; however, the processor sourced Address Latch Enable (ALE) and R'/W signals are generally sufficient for proper bus controller operation.) The memory clock, MCLK, is sourced by the processor and runs at 40 MHz. The 80 MHz MCLK2X is produced inside your bus controller circuit using a Digital Clock Manager (see sample code below). The bus controller must provide timing for fast SRAM, requiring only one MCLK cycle, as well as, slower flash memory that requires a total of four MCLK cycles. The processor WAITN signal is asserted back to the processor by the bus controller whenever the slower flash memory is being read (processor RW signal is low). We will assume that the flash memory resides in the low 2 GB address space (A31 asserted low), and that SRAM, along with the added internal IO ports reside in the upper 2 GB address space (A31 asserted high). (Note that A22:A30 are considered "don't care" for this design.)

The bus controller provides four 8-bit input ports and four 8-bit output ports, co-located at addresses selected by the MSEL15 signal (see decoder below) in the memory mapped I/O space. Use INPORT0-INPORT3 as the input signal names and OUTPORT0-OUTPORT3 as the output port signal names. Each port will be an 8-bit vector for a total of 64 signals. Assume no other devices/memory reside in MSEL15 address space.

The address bus, A(31:0), sourced by the processor, is 32 bits, and the data bus, DB(31:0) is 32 bits. The address bits are considered valid from the processor when the address latch enable, ALE, is asserted high. You should latch the address signals using a transparent latch inside your circuit and output address bits AOUT(31:2). Your circuit will use address bits A(1:0) and the Double-Byte Enable, DBE, signal to produce four byte-enable signals, BE0, BE1, BE2, and BE3, per the table shown below. (For Intel processors, these byte-enables are produced by the processor and permit half-word reads and writes.) On reads (R'/W signal low), the processor will select the byte or bytes that it needs; however, your circuit will produce the appropriate BEx signals for both reading and writing. When reading (R'/W signal low), bytes not requested by the BE signals will be tri-stated by your circuit.

DBE A1 A0 BE3 BE2 BE1 BE0

0 0 0 0 0 0 1

0 0 1 0 0 1 0

0 1 0 0 1 0 0

0 1 1 1 0 0 0

1 0 0 1 1 1 1

1 0 1 0 0 1 1

1 1 0 0 1 1 0

1 1 1 1 1 0 0

For memory reads and writes the circuit will decode four bits of the latched address bus, A18-A21 and generate 16 chip select signals, MSEL0-MSEL15, asserted low. These signals divide a portion of the upper and lower memory space into 64K word memory banks (presumably where 64K flash memories would be used). MSEL15 is used to select the four IO ports. Assume no other devices will reside in the MSEL15 address space. When an input or output port is addressed, the BE0/1/2/3 bits are used to determine if 8, 16, or 32 bits are read or written. For a read operation, a BEx of 0 will cause the corresponding data byte to be returned as tri-state. If A31 is low (reading flash memory), the circuit will generate a WAITN signal, asserted low, that permits 3 extra clock cycles (4 total MCLK periods) for flash memory reads, but provides no extra delay when SRAM (A31 high) or an IO port (MSEL15 asserted) is selected. The falling edge of the MREQN input signal indicates a new bus cycle and a valid address is on the address bus. Assume ALE asserts 10 ns after the falling edge of the MCLK, indicating a new memory cycle. The R’/W signal, declared RW in the Entity, selects reading (low) or writing (high). When writing and A31 is high, the bus interface circuit will generate a write enable, WEN, asserted low, for possible use by the memory devices. The address, BE0, BE1, BE2, BE3, data bus, and RW are passed on from your circuit to the memory as outputs. Use AOUT, BE0OUT, BE1OUT, BE2OUT, BE3OUT, DBOUT, and RWOUT as signal names for these signals. If desired, instantiate the Xilinx global Reset signal to provide any initial state settings in the circuit.

Xilinx Spartan and Virtex FPGAs contain Digital Clock Managers (DCMs) that are capable of multiplying and/or dividing clock signals with minimal clock skew. Choose a Spartan 3E device and instantiate a DCM that accepts the 40 MHz input MCLK and produces an 80 MHz 2x clock, MCLK2XOUT. (Refer to the Spartan DCM App Note on the Lecture web page). It is a good design practice to provide a 2x, or higher, clock to peripheral devices/interfaces that are connected to the bus controller. The 2x clock enables the device to set-up data early for processor reading on the next base clock edge or taking processor write data off the bus following a base clock edge.

MCLK

MCLK2X

ALE

R’/W

A31

WAITN

SRAM Read/Write Flash Memory Read

Port Read/Write

Note: MREQN signal is asserted low by the processor prior to the start of a memory cycle. The processor will hold the signal throughout most of the cycle. However, the bus controller can generally use only the ALE and R'/W signals to achieve proper operation.

Consider the following requirements for simulating the circuit. The test bench accesses the data bus as the processor, as well as, the flash or SRAM memory. When a memory read (flash or SRAM) occurs, the test bench will drive the DBOUT signals into the bus controller circuit, but the test bench must tri-state (HiZ) the DB signals to allow the ibus controller circuit to drive them. Likewise, when sending data out (write) on DB thru to DBOUT, you should tri-state (HiZ) the DBOUT signals in the test bench.

Simulation 1: Construct a test bench to provide the following:

Using repeated write cycles, load output port 0 with 0x00 (BE0=1) and output port 1 with 0xFF (BE1=1). Load output ports 2 and 3, BE2=BE3=1, in one bus cycle with 0x55AA. MSEL15 should assert for all of these writes. Only one MCLK cycle is required (WAITN does not assert).

Simulation 2: Construct a test bench that, at time 0, applies 0x00, 0xFF, 0x55, 0xFF to each input ports, respectively, then

· Reads input ports 1 and 2, BE1=BE2=1.

· Reads input port 0, BE0=1.

· Reads input port 3, BE3=1.

· Writes memory address 0xFFFFAA54 (A31 is high) with DB = 0x5555AAAA, four bytes w/ BE0:BE3=1. Be sure to tri-state DBOUT in the test bench. (Be sure WAITN does not assert.) Reads data memory address 0xFFFF55AA (two bytes w/ BE1=BE2=1) with DBOUT driven with 0xAAAA5555. Be sure to tri-state DB(31:0) so the circuit can drive the data bus back toward the CPU. The simulator should apply the DBOUT stimulus during the MCLK high time and hold for 13 ns past the next MCLK falling edge.

· Reads data memory address 0x000055A8, (A31 is low) (four bytes w/ BE0:BE3=1) with DBOUT driven with 0x5555AAAA. Operation requires four MCLK cycles. WAITN should assert and stay asserted until 12.5 ns before the fourth falling edge of MCLK.

· Reads two bytes (BE0=BE1=1) from data memory address 0x0000AA55 with DBOUT driven with 0xAA5555AA.

· Reads two bytes (BE1=BE2=1) from data memory address 0x0000AA56 with DBOUT driven with 0xAA5555AA.

· Reads two bytes (BE2=BE3=1) from data memory address 0x0000AA57 with DBOUT driven with 0xAA5555AA.

· Reads one byte (BE0=1) from data memory address 0x0000AA54 with DBOUT driven with 0xAA5555AA.

Provide a description and block diagram of the circuit along the VHDL circuit code, test benches, and timing windows. Mark up your timing windows to show the various simulation steps.

Extra credit opportunity: Use Text IO files to drive the VHDL test benches.

ECE5623 students must complete the following:

Add a 4-channel Pulse Width Modulation (PWM) unit to the bus controller. The unit resides in the MSEL14 address space (A31 low and A18:A21 = "1110"). Assume no other memory or IO devices are in this address space. The PWM output signals are PWMOUT0-PWMOUT3. Each PWM channel contains LOTIME and HITIME 32-bit registers that prescribe the number of 25 ns (40 MHz MCLK) clock pulses for the signal low time and high time, respectively. The LOTIME registers, channels 0-3, respectively, are located at addresses 0x00380000-0x0038000C (A31 low). Each register is four bytes. The HITIME registers, channels 0-3, respectively, are located at addresses 0x00380010-0x0038001C. Each register is four bytes. Each PWM channel has an enable/disable register, PWMENDIS. Writing a low byte (BE0 = 1) of 0x55 to the respective channel's address will enable PWM signal generation for that channel. Writing 0xAA to the low byte will disable the respective PWM signal. (Writing other data values to the registers will have no effect.) The respective PWMENDIS registers are located at 0x00380020-0x0038000C. When disabled, the PWMOUTx signal outputs should be low. When enabled, PWM signals start with the LOTIME, PWMOUTx low.

Provide test bench simulation(s) that set up and enable various PWM signal generations of differing periods and duty cycles. Make sure all four channels are generating signals simultaneously at some point in the simulation. Disable and change each channel's signal period and duty cycle at least once. Generate PWM signals in the microsecond range for at least two channels. Disable all signals at the end of the test bench.

Describe the test bench (using a table is helpful) and mark up the simulation waveform indicating the various signal generation steps.

Extra credit opportunity: Use Text IO files to drive the VHDL test benches.