Problem Set 4
ECE 551: Digital System Design and Synthesis
Spring 2003
Due Thursday, February 27. Grace period ends Tuesday, March 4 at 11:00 AM. Please note that this assignment is to be individual work and collaboration with others should be limited to understanding of the problem specifications. 100 points
1. Tasks and Functions (20 pts)
Media processors are embedded microprocessors designed specifically for the computational demands of image and video processing. To handle the workload of these signal-processing applications, a single instruction operated on multiple data (during a single clock cycle). Computer architects refer to this as SIMD (Single Instruction Multiple Data) instruction level parallelism. For this problem, you will design a vector adder, which uses saturation arithmetic. Each input vector and the result vector consists of four 8-bit operands.
a) Design a Verilog function that performs saturation, 2’s-complement addition on two 8-bit operands. Saturation addition differs from normal addition in that no overflow or underflow can occur. In the situation where overflow (or underflow) would normally occur, the maximum (or minimum) value that can be represented, + 27 – 1 (or - 27), is returned. Design tip: Although a testbench and simulation results are not required, it is suggested that the function be tested at this stage.
b) Design a Verilog task that uses your function from part a to implement a vector adder as described previously. Note: The entire vector addition takes a single cycle to perform.
c) Verify the whole design by applying the following operand combinations.
Operand A / Operand B32’h00_00_00_00 / 32’hFF_FF_FF_FF
32’h0F_0F_0F_0F / 32’hF1_F1_F1_F1
32’h89_AB_CD_EF / 32’h76_54_32_10
32’h1A_DD_2C_AD / 32’h3F_AD_4C_AB
32’h7F_7F_7F_7F / 32’h01_01_01_01
32’hFF_FF_FF_FF / 32’h80_80_80_80
Design tip: Your testbench should directly call the task. No intermediate module is needed. Submit all Verilog code and simulation results.
d) Is it valid to make part (a) a task and part (b) a function? Explain your answer.
A verbal specification for a weird electric coffee maker control is given on the last page of this assignment. The following problems refer to the specification of the coffee maker control. Read through all of the problems and the specification before beginning.
2. Algorithmic State Machine Chart (20 pts)
Draw a 4-state algorithmic state machine chart for the coffee maker control. The sequential circuit represented is to be a Moore type. An asynchronous reset signal should be provided for use on power up. Submit your ASM chart.
3. Verilog FSM Design (20 pts)
Write a Verilog description for the coffee maker control based on your ASM chart. Use a style with three parts: 1) state register, 2) combinational next state logic, and 3) output logic. Describe the state register and the next state logic using one always behavior for each. Describe the output logic by using a dataflow description (continuous assignment statements). Submit a printout of your debugged Verilog code.
4. Verilog FSM Design with Registered Outputs
Write a Verilog description for the coffee maker control with a register on the outputs. Use a style having 1) a combined state register and output register, 2) combinational next state logic and 3) combinational output logic. Describe each of the three components with an always behavior. This design is to be cycle-accurate with respect to the ASM chart and the design in Problem 2, i. e., the outputs are not to be delayed by a clock cycle compared to Problems 1 and 2.To accomplish this, use a case statement case (next_state) instead of case (state) to generate the outputs. Submit a printout of your debugged Verilog code.
5. Testbench and Simulation
Write a single testbench for the two coffee maker control designs. Apply an input sequence beginning with Reset that applies the equivalent of all combinations of states and input combinations to the ASM. Attempt to make the sequence minimum length by carefully tracing it out on the ASM chart and by using x values in the input combinations. For example, 11xxx represents CP = 1 and BN = 1 and 0xxxx represents CP = 0. Apply the input sequence to the designs in Problems 2 and 3, observing both the state and outputs of the two designs. Compare the state sequences and outputs from the two designs and discuss whether they are correct and given identical results. Submit a printout of your Verilog code, an annotated list file prepared as in last problem of Problem Set 3, and your discussion.
Coffee Maker Control Specification: The circuit to be designed here is based on the somewhat ridiculous specification that follows. The five inputs to the coffee maker control are:
Carafe present (CP) - a signal equals 1 if the carafe is present or is absent for no more than 15 seconds. Otherwise, if the carafe is absent for more that 15 seconds, CP equals 0 until the carafe has been replaced.
Brew now (BN) - a pushbutton that equals 1 when pressed and 0, otherwise.
Brew done (BD) - a signal generated by a separate circuit, the brew timer, which times the brewing period during which coffee is made; BD equals 0 during the brewing time and becomes 1 when the brewing time required has elapsed.
Min hold temperature (NHT) - a signal which equals 1 to indicate that the temperature for holding brewed coffee has dropped to the minimum value and that heat is to be applied, and equals 0, otherwise.
Max hold temperature (XHT) - a signal which equals 1 to indicate that the temperature for holding brewed coffee has risen to the maximum value and that heat is to be removed, and equals 0, otherwise.
In addition, when the power is turned on using a switch, the clock C begins operating and the Reset input is activated momentarily.
The two outputs from the coffee maker circuit are:
Heat (HT) - The heating element is on for HT equal to 1 and off for HT = 0.
Brew time (BT) - The synchronous brew timer counts down and provides the signal BD. While BT equals 0, the brew timer is continuously initialized to the brew time. When BT becomes 1, the brew timer begins counting down, and signal BD goes to 0. While BT = 1, the brew timer continues to count down to zero, at which BD goes to 1.
In summary, the input vector is (CP, BN, BD, XHT, NHT) and the output vector is (HT, BT).
The circuit operates as follows. As long as CP = 0 or BN = 0, the circuit remains in its initial state and the outputs HT and BT are both 0. When BN = 1 and CP = 1, the brew cycle begins. HT becomes 1, starting the brewing of the coffee, and BT becomes 1, starting the brew time countdown. BT remains at 1 until BD becomes 1 indicating that the brewing cycle is done. BD = 1 causes BT to become 0, initializing the brew timer to the brew time. The hold cycle begins with HT remaining at 1, holding the coffee temperature. On the other hand, if CP = 0, the control is initialized, stopping the brewing and hold operations. Within the hold cycle, as long as XHT= 0, HT remains 1. when XHT = 1, HT becomes 0 and remains at 0 until NHT = 1, at which time HT becomes 1. The latter cycle repeats as necessary to hold the coffee temperature. If the carafe is removed for longer than 15 seconds at any time during the brewing and holding cycles, CP becomes 0, returning the control and the brew timer to their initial states.
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