Sample FinalExamCMPEN 411

Name: ______

Student ID number (last 4 digits): ______

This is an OPEN BOOK and CLOSED NOTE exam.

  • Please write your name on every page and show all your work.
  • Write your solution clearly. You may use backside of each page for scratch but the solutions must be shown on the designated place near (below) each problem.
  • For each problem, assume the minimum size transistors of the 0.5um CMOS process available through MOSIS (n−type: Vt=0.9V, k’=50uA/V**2) (p−type: Vt=−0.9V, k’=−17uA/V**2), L=0.6um, W=0.9um.
  • When drawing a transistor circuit diagram, one may use AND, OR, INV, NAND, NOR, XOR logic gate symbols assuming they are thestatic CMOS gates.
  • Please ask if any of the problems (and assumptions) is not clear.

______

  1. Givena logic implementation and an input signal shown below, show a logic simulation output of the circuit assuming each NAND gate has delay of 1.0 nsec.
  1. Determine the voltages Va, Vb, and Vc of the following circuit. Assume the initial condition Va=Vb=Vc=0V.

  1. Assuming the design rule for NCSU_Tech_ami060.5umCMOStechnology,whatarethe smallestsize:

(a) Fill-in the table below:

Poly wire width / um
Transistor channel length / um
Transistor channel width / um
N diffusion width / um
Metal 1 width / um
Metal 3 width / um

(b) List two factors that ultimately limit the smallest feature size in VLSI technology:

  1. Calculate the drain current and the equivalent resistance of the following minimum size transistor (L=0.6um, W=0.9um drawn) circuits.
  1. Size the transistors in the following circuit to reduce the worst case delay. Make the fall & rise time equal to each other and comparable to the fall time of an inverter with minimum size NMOS transistor. Show transistor size in width/length (W/L), in scalable unit ratio (or lambda), next to each transistor. Assume the minimum size N:P ratio of 1:3

  1. Shown at the right is the voltage transfer

curve (DC characteristic curve) of a 2-input

NAND gate with minimum size transistors.

Determine the following parameters and

noise margins:

Vin-low ______volt

Vin-high ______volt

Vout-low ______volt

Vout-high ______volt

NMlow ______volt

NMhigh ______volt

  1. Sketch the Hspice output waveforms of OUT1, OUT2, and OUT3 for the given input IN shown below. You may approximate the time scale, but be sure to show differences among OUT1, OUT2, and OUT3 timing. Assume each transistor channel width as indicated, and assume all transistor channel length the same.

(a) Sketch the timing

(b) Sketch the VTC curves for the above inverters and label each one: OUT1, OUT2, and OUT3.

  1. Consider the logic function F= AB+C(A+B). Give the transistor circuit diagram of a single static CMOS gate that implements the function F. Full credit given to the design with fewest transistors. Available input signals are: A, B, and C.

Total transistor count: ______

  1. We are using Cadence Virtuoso CAD tool. What are the tasks that the chip designer can accomplish with the tool? List at least 5 tasks that are essential for a chip design.
  1. What are the two cost categories that adds up to the chip cost? List 7 major cost factors for achip.
  1. List three items which a circuit and layout design engineer can do to lower the cost of his/her chip.
  1. What is Moore’s Law? State the Law in a few sentence. Can you say the same for the chip speed? Why or why not? Can you say the same for the chip power dissipation? Why or why not?
  1. What are the three main limiting factors for Moore’s Law to continue for next 10 years?
  1. Shown below is the non-inverting buffer circuit. Draw the voltage transfer curve (DC characteristic curve). Then determine the following parameters and noise margins:

Vin-low ______V Vin-high ______V

Vout-low ______V Vout-high ______V

NM-low ______V NM-high ______V

  1. Calculate the drain current (Id), the output voltage (Vout), and the equivalent resistance (Requ) of the transistor (drain to source) of the following minimum size transistor circuits. Show your work.

(a)

Vdd = 5V

Vin = 0.5V

Id = ______mA

Vout = ______V

Requ = ______ohm

(b)

Vdd = 5V

Vin = 5V

Id = ______mA

Vout = ______V

Requ = ______ohm

  1. List 5 different ways to reduce leakage power.
  1. List 5 different ways to reduce short-circuit power.
  1. List 5 different ways to reduce dynamic power.
  1. List 3 potential problems due to the charge sharing.
  1. Do the following charge sharing calculation: Calculate the final output voltage of the two capacitors in parallel, 5pF and 2pF. The 2pF capacitor was initially charged to 5V and the 5pF capacitor was initially charged to 0V. Is the result become problem? Why or why not?
  1. Understanding how the clock feed-through occurs, list 3 different ways to reduce clock feed-through.
  1. Write a simplest Boolean expression of the following CMOS logic circuit. Also draw an equivalent logic diagram using digital gate symbol(s).

Z = ______

  1. List a unique advantage of an np-CMOS logic circuit.
  1. For static CMOS logic style, can we build 2 input AND gate with 2 NMOS transistors and 2 PMOS transistors? Why or why not?
  1. For the Homework 2, you have designed an 8-bit ripple carry adder circuit and simulated the circuit with Hspice to determine the worst case delay. The worst case add time was 2.5ns with Vdd=5.0V. If you set Vdd=3.3V and re-simulate (Hspice) the same circuit, what will be the worst case add time?
  1. Your course project chip designed with AMI 0.6um CMOS has been fabricated and tested with 5V power. The maximum clock frequency of 100MHz was observed while the chip was fully functioning. Also the power dissipation of 200mW was observed. Please answer the following questions:

(a) Without the pad, your project core is 0.9mm by 0.9mm. The same layout design is scaled and fabricated with AMI 0.3um CMOS technology. What is the actual die size of your project core?

(b) For the same layout design fabricated with AMI 0.3um CMOS technology, what would you expect the maximum clock frequency to be?

(c) For the same layout design fabricated with AMI 0.3um CMOS technology, what would you expect the power dissipation at the maximum clock frequency?

(d) To fabricate the same layout design in AMI 0.6um CMOS technology and AMI 0.3um CMOS technology with scaling, which one is more expensive? Why?

  1. Consider the following three power consumption components of CMOS circuit:

(1) Direct−path current (short circuit dissipation)

(2) Static consumption

(3) Dynamic consumption

Which component(s) is (are) independent of the signal switching activity? ______

Which component(s) is (are) independent of the signal rise & fall time? ______

Which component(s) is (are) dependent on the signal rise & fall time? ______

Which component(s) is (are) independent of the load capacitance? ______

Which component(s) is (are) independent of the transistor size? ______

  1. Consider the following four implementations of a 64 bit adder.

(A) Ripple carry adder

(B) Pipelined ripple carry adder

(C) Carry Lookahead adder

(D) Bit serial adder

Which implementations (choose two) are more suitable for

high speed chip? ______

small size chip? ______

less power consuming chip? ______

cheaply produced chip? ______

Which implementation is most difficult to design? ______

Which implementation is most difficult to use? ______

  1. List four clear advantages of SRAM over DRAM:

(1)

(2)

(3)

(4)

  1. List four clear disadvantages of SRAM over DRAM:

(1)

(2)

(3)

(4)

  1. List the following multipliers in order of its multiply time (time it takes to multiply two numbers). Two numbers are 128 bit each, unsigned binary numbers. Start the list with the fastest multiplier first.

Booth Multiplier, Wallace-Tree Multiplier, Carry-Save Multiplier, Array Multiplier, 4-to-2 Compressor Multiplier.

(1)

(2)

(3)

(4)

(5)

  1. Tri-state non-inverting output driver is shown below. Draw the optimized logic circuit for the control logic box shown below.

Gp = ______

Gn = ______

  1. List five ways to make the class project, the 8 bit RISC microcontroller, run faster: