Syllabus: CPE/EE 422/522
Advanced Logic Design, Summer 2003
Office: 217-L Phone: (256) 824 6830
Lab Instructors: / Mr. Pan, Zexin Email:
Phone: (256) 824-3483 Office: Eb242d
Preston, Chidebelu Email:
Phone:825-6317 Office: EB142
Time and Place: / Lectures: MW 5:00 PM - 7:00 PM, Engineering Building 207
Lab session #1: Monday 3:00 - 5:00 PM, Mr. Zexin Pan.
Lab session #2: Tuesday 7:00 - 9:00 PM. Mr. Chidebelu Preston.
Lab session #3: Wednesday 3:00 - 5:00 PM, Mr. Zexin Pan.
Lab session #4: Thursday 7:00 - 9:00 PM, Mr. Chidebelu Preston.
Lab session #5: Friday 10:00 – 12:00 AM, Mr. Chidebelu Preston.
Course Web Page: / www.ece.uah.edu/~milenka/cpeee_422522_03S/
Office Hours: / MW: 7:00 – 8:00 PM
Textbook: / Digital Systems Design Using VHDL, Charles H. Roth, Jr., PWS Publishing, 1998 (ISBN: 0-534-95099-X).
Reference Text(s): / Fundamentals of Digital Logic with VHDL Design, Stephen Brown, Zvonko Vranesic, McGraw-Hill, 2000 (ISBN: 0-07-012591-0).
Prerequisites: / EE 202 Introduction to Digital Logic Design
Course Description: / Advanced concepts in Boolean algebra, use of hardware description languages as a practical means to implement hybrid sequential and combinational designs, digital logic simulation, rapid prototyping techniques, and design for testability concepts. Focuses on the actual design and implementation of sizeable digital design problems using representative Computer Aided Design (CAD) tools.
Tentative Schedule: / W#1: Introduction to Combination Logic / Boolean Algebra
W#2: K-maps, Designing with NAND/NOR gates, 3-state logic and buses, memories, PAL’s, PLA’s
W#3-#4: Flip-flops and Lathes, Mealy and Moore Sequential Networks, Sequential Network Timing, Equivalent states, Using SM charts,
W#4-#9: Introduction to VHDL
W#10: CPLDs and FPGAs, Introduction to Hardware Testing
Grading Policy: / 1. Lab Assignments 55%
2. Midterm Exam 15%
3. Final Exam 30%
Labs must be submitted at the beginning of the lab on the day they are due. Labs submitted more than one week late will not be graded. Late labs will be penalized 20% for the first day late, and 10% per day thereafter. No make-up exam will be given unless you make arrangements with the (lab) instructor at least 24 hours in advance. All requests for a re-grade must be submitted in writing within a week of the assignment being returned. No assignment will be re-graded after one week. Please let me know immediately if I have added up your score incorrectly.
Grades will be determined on a 60-70-80-90 straight scale. On occasion I may use a slightly lower scale, but I will never raise the requirements.
Lab Assignment / The Laboratory Assignment component of the grade will be composed of simulation, labs, practical exam, and for graduate students a separate graduate design project. SIMULATIONS represent small assignments, which utilize the Symphony EDA or Altera simulators to demonstrate the functionality of the design. The LABs represent complete digital designs, which are to be actually implemented on rapid prototyping hardware that is present within the Rapid Prototyping Laboratory, RPL. The practical EXAM, is a short exam, which measures the students ability to implement simple designs using the CAD tools. Graduate students will be given an additional graduate project (GRAD). The instructor will supply a default graduate laboratory assignment to the class. The assignment of credit for each of these components is shown below:
cpe/ee 422 cpe/ee 522
1. Simulation 10% 10%
2. Lab#1 10% 10%
3. Lab#2 5% 5%
4. Lab#3 10% 5%
5. Lab#4 10% 5%
6. Lab Exam 10% 10%
7. Grad project - 10%
Homeworks / Students are encouraged to independently or in small groups work the following homeworks. Due to the size of the class none of these homeworks will be taken up and graded. Complete solutions will be available on the class web site.
Tentative Schedule of Important Class Dates / 1. Midterm Exam - June 30, 2003
2. Laboratory Exam - July 21, 2003 - July 25, 2003
3. Final Exam - July 30, 2003, 6:30 PM -- 9:00 PM.
I reserve the right to change the above schedule based upon the needs of the course.
Academic Honesty: / Discussing the homework and laboratory assignments with other students is encouraged, as that is one of the best ways to learn the material. But the work submitted should be your own.
All students will be trusted to pursue their academic careers with honesty and integrity.
Students are expected to fully conform to the UAH policies concerning academic misconduct as outlined in Article III (starting on page 91) of the 2000-2001 UAH Student Handbook.