DUBLIN CITY UNIVERSITY

SEMESTER ONE REPEAT EXAMINATIONS 2007

MODULE: Digital Circuits and Systems (EE201)

COURSE: B.Eng in Info and Communications Engineering

B.Eng in Mechatronic Engineering

B.Eng in Electronic Engineering

B.Eng in Digital Media Engineering

YEAR: 2 (two) and 3(three)

EXAMINERS: Mr David Bermingham (ext. 7692)

Dr. R. Millar

Dr. F. Derek

TIME ALLOWED: 2 Hours

INSTRUCTIONS: Answer FOUR questions. All questions carry equal marks

Requirements for this paper / Log Table
Please tick (X) as appropriate / Graph Paper
Attached Answer Sheet
Statistical Tables
Floppy Disk
Actuarial Tables

THE USE OF PROGRAMMABLE OR TEXT STORING CALCULATORS IS EXPRESSLY FORBIDDEN

Please note that where a candidate answers more than the required number of questions, the examiner will mark all questions attempted and then select the highest scoring ones.

PLEASE DO NOT TURN OVER THIS PAGE UNTIL YOU ARE INSTRUCTED TO DO SO


Question 1

1(a) / Design a 1-line to 4-line demultiplexer using logic gates and briefly describe its operation. How can this demultiplexer be used as a 2-line to 4-line decoder? / [10 marks]
1(b) / Implement the following logic function using only 4-line to 1-line multiplexers:
. / [15 marks]

[Total marks: 25]

Question 2

2(a) / Compare the serial and the parallel interfaces between computers and peripherals by indicating their advantages and disadvantages. / [8 marks]
2(b) / Draw a block diagram of an ACIA type serial interface controller. / [7 marks]
2(c) / Describe the function of each block of the diagram drawn in Q2 b) / [10 marks]

[Total marks: 25]

Question 3

3(a) / Compare the three possible output configurations possible when using TTL circuits. Compare and contrast the methods when applied to data bussing. / [12 marks]
3(b) / Describe, using a diagram, the structure and operation of a CMOS NAND gate. Why does its power dissipation depend on the frequency of operation? / [8 marks]
3(c) / A 74LS00 NAND gate is used to drive similar NAND gates. Given the following parameters for a 74LS00 NAND, IIH=20µA, IOH=-0.4mA, IIL=-0.4mA, IIH=8mA. Determine the fanout of a single 74LS00 NAND gate. / [5 marks]

[Total marks: 25]

Question 4

4(a) / An 8-bit ripple carry adder is constructed using NAND logic. If the propagation delay for a NAND gate is 250 pS what is the maximum addition time for the adder? / [5 marks]
4(b) / Outline an algorithm for addition of two floating-point numbers. / [8 marks]
4(c) / Multiply using the Booth algorithm +8 and –12. Design the hardware required for this multiplication. Indicate the major signals required. / [12 marks]

[Total marks: 25]

Question 5

5(a) / Briefly describe the dynamic RAM cell and its operation. How does it compare with a single static RAM cell in terms of area, speed, control circuitry and power / [15 marks]
5(b) / Compare the architecture of PROM and PLA and state the advantages, disadvantages and suitable applications of each? / [10 marks]

[Total marks: 25]

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