SimpComp Computer Architecture
Computer Architecture Overview
The SimpComp computer is a simplified version of a more powerful embedded system controller. It is composed of a 16-bit CPU, 64k byte memory module, a memory management unit (MMU), a clock-timer, an interrupt controller, and up to seven I/O devices. Figure 1 shows the overall architecture of the SimpComp. The control lines ACK, INT, MS and the IRQ-x lines will be explained below. The address bus to memory is a full 16-bits. The extension address bus for I/O is the lower 8 bits of the full address bus. The data bus is 8 bits. The memory module is byte-addressable so two memory accesses are needed to fetch a full 16-bit word.
The SimpComp is a load/store architecture, having much in common with more sophisticated RISC-type architectures. It only has three addressing modes for load/store (four for load) and branch instructions. These are: direct, PC-offset, and register-indirect (plus immediate for load). Indexed and base-relative addressing are handled in software. There is a set of instructions for pushing and popping data to/from a system stack. To use these instructions, the programmer must dedicate register RF to be the stack pointer. It is the programmer’s responsibility to see to it that this register is properly initialized at startup (Note: if BOS/EOS is being used, the stack is initialized at FFFFh and grows down toward low memory – into the USR area, in which case stack overflow must be checked by the software).
Fig. 1 Overall computer architecture for the SimpComp.
Each element in the SimpComp is described below. The RESET is just a button that can cause the CPU to enter a starting state (PC 0; flags 0, etc.).
CPU
The SimpComp central processing unit (CPU) is shown in Figure 2. The CPU contains sixteen, 16-bit general purpose registers, a 16-bit arithmetic/logic unit (ALU), a control unit, a 32-bit instruction register (IR), a program counter register (PC), a process status word register (PSW), a memory data register (MDR), a memory address register (MAR), a clock (CLK) and a 16-bit wide internal bus for the transfer of data/addresses between the various components. Not shown in the figure are lines comprising the control bus, though an external interface from the control unit to the external control bus is shown. Various control points along the bus are shown as dark black squares on the bus lines. Crossing lines are used to indicate the number of wires (usually 16).
Figure 2. SimpComp CPU and its connections to the external buses.
Components of the CPU
Internal Bus
The internal bus is comprised of a single shared bus of 16 lines for both data and addresses. A separate control bus (not shown in the diagram) connects the control unit with each component and with the bus direction selection points (large dots on the bus lines are n-way switches). The main bus interfaces with the instruction register (below) via four separate 8-bit lines from the low-order 8 lines of the internal bus.
Clock (CLK)
A single clock provides a clocking signal used by the control unit to sequence through control programs for each instruction (see microarchitecture).
Control
The control unit interprets the operation code in the high-order byte of the instruction register (below). It then sets appropriate control lines in the right sequence to control the flow of data (operand data and address data) through the bus and to control the behavior of the various components (registers, ALU, etc.).
Executive Register (ER)
This register is used to create a protected mode of operation for operating systems. The ER can be loaded, during system boot, with the high address boundary of the operating system code segment. Any value greater than zero in this register will set the computer into executive mode. In this mode of operation certain instructions such as HALT or IN/OUT and interrupt management instructions can only be executed from code within the protected segment. All other memory is considered user program memory. This feature allows SimpComp to run a reasonably secure operating system. EOS provides some aspects of this feature. When EOS is loaded from the BOS service routine (see Programmer’s Guide), the BOS automatically sets the ER, using the SETE instruction, and after that time, the instructions tagged as only operating in executive mode (see table below) can only be invoked by the EOS/BOS. SimpComp is initialized with ER = 0, i.e., not in executive mode. If the user replaces the EOS with another OS, the new OS will need to reset the value in the ER according to its needs.
When the computer is operating in executive mode, any attempt by a user program to execute one of the EM instructions is trapped by the CPU and results in the execution of a BOS interrupt service call (software interrupt). The user program is terminated and control reverts to the EOS (or supplied OS).
Registers
There are sixteen 16-bit registers, numbered 0 to F (hex). The registers are referenced by the capital letter ‘R’ followed by the number, e.g., R0. Registers are divided into low and high-order bytes. Low-order bytes are used in byte-mode operations. All sixteen registers can be used as general purpose registers, however several registers have additional special-purpose assignments under certain operations. RF (#16) is also used as a stack pointer for PUSH and POP operations. RE (#15) is used to hold the remainder of a 16-bit division (DIV).
General reference to an arbitrary register is denoted by Rx or Ry, where x, y can be any hexadecimal number between 0 and F.
Arithmetic/Logic Unit (ALU)
The ALU contains logic to support the arithmetic and logic operations given in the instruction set. The first indicated operand in an instruction format is copied to the A buffer of the ALU. This will be the augend, minuend, multiplicand or dividend for arithmetic or the register value to be incremented or decremented. The second operand is transferred to the B buffer in dyadic operations.
Program Counter (PC)
The program counter is a register that points to the next instruction opcode to be fetched from memory. The PC is updated after the opcode is loaded and decoded for the number of additional bytes that need to be fetched for the current instruction, but before the instruction is executed.
Process Status Word (PSW)
The process status word contains sub-fields used to maintain a record of the state of the processor. The highest-order nybble, PSW[F..C], contains the flags, Carry, Negative, Zero and Overflow. The next lower three bits PSW[B..9] hold the current I/O bank number (0 – 7). The next three bits are reserved for future use. Bits PSW[5..3] contain the interrupt service vector of the currently pending interrupt (if any). Bits PSW[2..0] contain a bit pattern that designates masking of interrupts. The instructions SETI and GETI allow a program to mask specific interrupts. Setting these three bits to 111 (1Fh) disables all interrupts (except for the reset signal). This can be done using the DI instruction. Interrupts can be unmasked individually with SETI or all can be enabled using the EI instruction.
Instruction Register (IR)
Instructions are loaded into the 32-bit instruction register. There are instructions that require only one byte as well as those that require all four bytes. Instruction formats are given below. Each sub-field of the IR is loaded independently as needed. Those fields that provide data or addresses can be written back to the bus as needed. See Instruction Formats (below) for an explanation of the byte fields in the IR.
Memory Address Register (MAR)
This is a buffered register for interfacing the internal bus to the external address bus.
Memory Data Register (MDR)
This is a buffered register for interfacing the internal bus to the external data bus. The external data bus is 8 bits wide whereas the MDR is 16 bits wide. For word-mode load or store operations, the MDR receives or transfers two bytes. The high-order byte of a word is first fetched and loaded into the low-order 8 bits of the MDR. The byte is then shifted left by 8 bits and the second byte is fetched. This operation is reversed in the case of a store of a word.
Memory Management Unit
This unit is essentially a switch that is activated by the MS signal from the CPU. When the MS signal is asserted, the MMU routes all 16 lines of the address bus to the memory module. When MS is not asserted, the MMU routes the lower 8 lines of the address bus to the I/O modules. The MS signal is asserted on any LOAD/STORE instruction execution but is not asserted for IN/OUT instructions.
Memory Unit
The memory unit consists of 65,536 (64k) bytes of memory cells. The first 8k (213) of memory is a ROM containing the BOS (basic operating system). RAM starts at 2000h. From 2000h to 203F (64 bytes) is the interrupt vector table (fixed). Starting at 2040h is the Extended Operating System (EOS), if used, which runs to 403Fh. The USR (user) program area then starts at 4040h. The memory map for the SimpComp is shown in Figure 3.
The SimpComp evaluation board comes with the BOS operating system installed in ROM. The BOS includes a function for loading the EOS (extended OS) from the disk device (or host system). See the Programmer’s Guide for complete description of the BOS/EOS.
When the SimpComp is embedded in a fielded application the BOS ROM is generally replaced by an application specific ROM. On reset, the PC is automatically set to address zero and instruction fetching commences from that location.
Figure 3. The memory map for the SimpComp computer. Memory from 0h to 1FFFh is ROM and contains the Basic Operating System (BOS).
Note that the first eight addresses (16 bytes) of the interrupt vector table are reserved for the hardware interrupts managed by the Interrupt controller (below). The next 8 vectors are reserved for software interrupts handled by the BOS. The next 8 vectors are reserved for use by the EOS. The final 8 vectors are reserved for future use.
Input/Output
SimpComp can have up to sixteen separate I/O devices installed. Only seven devices can be interrupt-driven however. Each device is assigned a unique I/O address using 4 bits stored in the PSW, bits 8 through 11. These bits can be set from a designated register, or gotten to the register with the SETP and GETP instructions. The I/O device address is carried in the upper four bits of the lower eight bits of the address bus (the lines from the MMU devoted to I/O).
Each I/O device can have up to 16 port numbers (internal registers) assigned to it. Thus an I/O operation consists of first setting the I/O device address in the PSW bits, followed by an appropriate IN or OUT instruction. The port number operand of these instructions forms the low four bits of the address bus. It is possible to have more than one device represented by the high four bits as long as there are unique low-order bit addresses, among the sixteen possible, assigned to registers in the different devices.
The Timer (see below) is not a standard I/O device as such, but has been assigned to I/O device 0 (interrupt request line 0). The timer is programmable, meaning that the CPU can access registers within the timer to control its subsequent behavior.
By default – and as used in the BOS – I/O device 1 is the standard input device, STDIN, (i.e., keyboard) and device 2 is the standard output device, STDOUT, (i.e., display unit). Other devices include serial I/O, SIO, and parallel I/O, PIO, units as needed in the application. In general there will be at least one SIO and one PIO device.
See the detailed specification sheets for the keyboard controller, display controller, SIO and PIO devices for interfacing and configuration details.
Interrupt Controller
The interrupt controller acts as an intermediary between the various external devices (timer and I/O) and the CPU. Each device that requires interrupt processing for service (8 in all) are assigned interrupt request numbers, IRQ-x, where x is 0 to 7. When a device needs service, it asserts an IRQ signal, which notifies the interrupt controller. The controller arbitrates priorities between devices and sends an INT signal to the CPU. After sending the INT signal, the controller then puts the interrupt service vector (ISV) onto the data bus. The CPU uses the ISV as the offset into the interrupt service table (see memory map above) where the address of the appropriate service routine will be found. The value in the table at the ISV offset is loaded into the PC and execution branches to that location (the PSW is pushed onto the system stack to preserve state). The CPU also sends an ACK signal to the controller to indicate acknowledgement of the interrupt. The controller will use this signal to set up the next pending interrupt (if a new IRQ signal has been asserted). If the controller receives a new IRQ of higher priority after the ACK signal, the controller will save the current IRQ being serviced and assert the new interrupt and go through the same steps as above. In this way, the CPU can be interrupted by the highest pending interrupt and branch to the appropriate service routine. As the CPU completes service of each interrupt an EOI signal is sent to the controller (in the form of a second ACK). This signal notifies the controller that it can revert to the last pending interrupt IRQ if needed.
See the interrupt controller specification sheet for details on the operation and configuration of the interrupt controller.
Timer
The timer is actually a multiple timer device. There are four timers available. It is programmable by the CPU to provide timing signals and interrupts at specified intervals. There is only one IRQ assigned to the timer so the interrupt service routine has to determine which timer set off the interrupt. In the event of multiple, simultaneous timer events, the timer will, like the interrupt controller, keep track of the relative priorities of the timers and assert the code of the highest priority timer on the data bus. Timer priorities are the inverse of the timer number, i.e., timer TIM0 has the highest priority.
See the timer specification sheet for details on operation and configuration of the timer.
Instruction Formats
Instructions may take one, two, three or four bytes depending on the operand requirements. Operands are of five types. These are: register designation, operand address, PC offset, immediate operand (either byte or word), and port number. Interpretation of field contents is encoded in the opcode bit pattern. There are nine fetch formats. Below are the formats with their field representations.
Format 0: load 1 byte
OpcodeFormat 1: load 2 bytes, register designators
Opcode / dest.,Rx / src., RyFormat 2: load 2 bytes, register, port#
Opcode / Rx / portFormat 3: load 2 bytes, offset
Opcode / offsetFormat 4: load 3 bytes, register designation, offset address of operand
Opcode 10 / Rx / unused / offsetFormat 5: load 3 bytes, register designation, immediate byte operand
Opcode 10 / Rx / unused / immediateFormat 6: load 3 bytes, immediate word operand
Opcode 10 / immediate high / immediate lowFormat 7: load 4 bytes, register designation, address of operand
Opcode 11 / Rx / unused / address high / address lowFormat 8: load 4 bytes, register designation, immediate operand
Opcode 11 / Rx / unused / immediate high / immediate lowOpcode Decoding
Below are the bit patterns that are used to decode the operation codes for the SimpComp. Bit patterns are based on the operation type. These are: load/store, ALU, branch and call, mixed and I/O, and miscellaneous. Each operation type (determined by the high-order several bits) decodes the subsequent (remaining low-order bits) somewhat differently. However the addressing modes, byte/word mode and byte count to fetch are relatively consistent in the bit number used to code.
Load/Store Operations
Formats: 1, 3, 4, 6 & 7
ALU Operations
Format 1. Monadic operations ignore second register designator
All ALU operations are 2-byte instructions so the byte count bit is always 0.
Branch and Call Control
Formats: 1, 3 & 6
Mixed and I/O Operations
Formats: 0 & 1
Miscellaneous Operations
Formats: 0 & 1
Addressing Modes
SimpComp is a byte-addressable computer. This means that the computer can load or store either a single byte or a full word. The latter requires two memory accesses. All load/store instructions come in either byte or word mode as designated by bit 2 in load/store/move instructions. Addressing modes apply to the load/store and some modes to branch control operations. The addressing modes are: