1.1 D FLIP FLOP USING CASE

PROGRAM:

Module d(

input D,

input clk,

outputreg Q

);

always @(posedge clk)

begin

case(D)

1'b0: Q<=1'b0;

1'b1: Q<=1'b1;

endcase

end

endmodule

TEST BENCH:

module tb_dff;

// Inputs

reg D;

regclk;

// Outputs

wire Q;

// Instantiate the Unit Under Test (UUT)

dffuut (

.D(D),

.clk(clk),

.Q(Q)

);

initial begin

// Initialize Inputs

D = 0;

clk = 0;

// Wait 100 ns for global reset to finish

#100;

D=0;

clk=1;

#100;

D=1;

clk=0;

#100;

D=0;

clk=0;

#100;

D=1;

clk=1;

#100;

D=0;

clk=1;

#100;

D=0;

clk=0;

#100;

D=0;

clk=1;

#100;

// Add stimulus here

end

endmodule

RESULT:

RTL SCHEMATIC:

TECHNOLOGY SCHEMATIC:

TIMING REPORT:

TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT

GENERATED AFTER PLACE-and-ROUTE.

Clock Information:

------

------+------+------+

Clock Signal | Clock buffer(FF name) | Load |

------+------+------+

clk | BUFGP | 1 |

------+------+------+

Asynchronous Control Signals Information:

------

No asynchronous control signals found in this design

Timing Summary:

------

Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: 1.378ns

Maximum output required time after clock: 5.248ns

Maximum combinational path delay: No path found

Timing Detail:

------

All values displayed in nanoseconds (ns)

======

Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'

Total number of paths / destination ports: 1 / 1

------

Offset: 1.378ns (Levels of Logic = 1)

Source: D (PAD)

Destination: Q (FF)

Destination Clock: clk rising

Data Path: D to Q

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

------

IBUF:I->O 1 0.824 0.357 D_IBUF (D_IBUF)

FD:D 0.197 Q

------

Total 1.378ns (1.021ns logic, 0.357ns route)

(74.1% logic, 25.9% route)

======

Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'

Total number of paths / destination ports: 1 / 1

------

Offset: 5.248ns (Levels of Logic = 1)

Source: Q (FF)

Destination: Q (PAD)

Source Clock: clk rising

Data Path: Q to Q

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

------

FD:C->Q 1 0.495 0.357 Q (Q_OBUF)

OBUF:I->O 4.396 Q_OBUF (Q)

------

Total 5.248ns (4.891ns logic, 0.357ns route)

(93.2% logic, 6.8% route)

======

Total REAL time to Xst completion: 5.00 secs

Total CPU time to Xst completion: 4.63 secs

-->

Total memory usage is 146772 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 0 ( 0 filtered)

Number of infos : 0 ( 0 filtered)

1.2 SR FLIP FLOP USING CASE

PROGRAM:

module srff(

input s,

input r,

inputclk,

outputreg q

);

always @(posedgeclk)

begin

case({s,r})

2'b0_0:q<=q;

2'b0_1:q<=1'b0;

2'b1_0:q<=1'b1;

2'b1_1:q<=1'bz;

endcase

end

endmodule

TEST BENCH:

moduletb_srff;

// Inputs

reg s;

reg r;

regclk;

// Outputs

wire q;

// Instantiate the Unit Under Test (UUT)

srffuut (

.s(s),

.r(r),

.clk(clk),

.q(q)

);

initial begin

// Initialize Inputs

s = 0;

r = 0;

clk = 0;

// Wait 100 ns for global reset to finish

#100;

s=0;

r=0;

clk=1;

#100;

s=0;

r=0;

clk=0;

#100;

s=0;

r=1;

clk=1;

#100;

s=0;

r=1;

clk=0;

#100;

s=0;

r=0;

clk=1;

#100;

s=0;

r=0;

clk=0;

#100;

s=1;

r=0;

clk=1;

#100;

s=0;

r=0;

clk=0;

#100;

s=1;

r=1;

clk=1;

#50;

s=1;

r=0;

clk=0;

#25;

s=1;

r=0;

clk=1;

#25;

// Add stimulus here

end

endmodule

RESULT:

RTL SCHEMATIC:

TECHNOLOGY SCHEMATIC:

TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT

GENERATED AFTER PLACE-and-ROUTE.

Clock Information:

------

------+------+------+

Clock Signal | Clock buffer(FF name) | Load |

------+------+------+

clk | BUFGP | 2 |

------+------+------+

Asynchronous Control Signals Information:

------

No asynchronous control signals found in this design

Timing Summary:

------

Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: 2.480ns

Maximum output required time after clock: 5.248ns

Maximum combinational path delay: No path found

Timing Detail:

------

All values displayed in nanoseconds (ns)

======

Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'

Total number of paths / destination ports: 8 / 4

------

Offset: 2.480ns (Levels of Logic = 2)

Source: r (PAD)

Destination: Mtridata_q (FF)

Destination Clock: clk rising

Data Path: r to Mtridata_q

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

------

IBUF:I->O 3 0.824 0.559 r_IBUF (r_IBUF)

LUT2:I0->O 2 0.561 0.380 Mtridata_q_not00011 (Mtridata_q_not0001)

FDE:CE 0.156 Mtridata_q

------

Total 2.480ns (1.541ns logic, 0.939ns route)

(62.1% logic, 37.9% route)

======

Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'

Total number of paths / destination ports: 2 / 1

------

Offset: 5.248ns (Levels of Logic = 1)

Source: Mtridata_q (FF)

Destination: q (PAD)

Source Clock: clk rising

Data Path: Mtridata_q to q

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

------

FDE:C->Q 1 0.495 0.357 Mtridata_q (Mtridata_q)

OBUFT:I->O 4.396 q_OBUFT (q)

------

Total 5.248ns (4.891ns logic, 0.357ns route)

(93.2% logic, 6.8% route)

======

Total REAL time to Xst completion: 4.00 secs

Total CPU time to Xst completion: 3.83 secs

-->

Total memory usage is 161108 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 0 ( 0 filtered)

Number of infos : 0 ( 0 filtered)

1.3T FLIP FLOP USING CASE

PROGRAM:

moduletff(

input t,

inputclk,

outputreg q

);

initial q<=1;

always @(posedgeclk)

begin

case(t)

1'b0:q<=q;

1'b1:q<=~q;

endcase

end

endmodule

test bench:

moduletb_tf;

// Inputs

reg t;

regclk;

// Outputs

wire q;

// Instantiate the Unit Under Test (UUT)

tffuut (

.t(t),

.clk(clk),

.q(q)

);

initial begin

// Initialize Inputs

t = 0;

clk = 0;

// Wait 100 ns for global reset to finish

#100;

t=0;

clk=1;

#100;

t=1;

clk=0;

#100;

t=1;

clk=1;

#100;

t=1;

clk=0;

#100;

t=0;

clk=1;

#100;

// Add stimulus here

end

endmodule

result:

rtl schematic:

technology schematic:

TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT

GENERATED AFTER PLACE-and-ROUTE.

Clock Information:

------

------+------+------+

Clock Signal | Clock buffer(FF name) | Load |

------+------+------+

clk | BUFGP | 1 |

------+------+------+

Asynchronous Control Signals Information:

------

No asynchronous control signals found in this design

Timing Summary:

------

Speed Grade: -5

Minimum period: 1.991ns (Maximum Frequency: 502.273MHz)

Minimum input arrival time before clock: 1.337ns

Maximum output required time after clock: 5.271ns

Maximum combinational path delay: No path found

Timing Detail:

------

All values displayed in nanoseconds (ns)

======

Timing constraint: Default period analysis for Clock 'clk'

Clock period: 1.991ns (frequency: 502.273MHz)

Total number of paths / destination ports: 1 / 1

------

Delay: 1.991ns (Levels of Logic = 1)

Source: q (FF)

Destination: q (FF)

Source Clock: clk rising

Destination Clock: clk rising

Data Path: q to q

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

------

FDE:C->Q 2 0.495 0.380 q (q_OBUF)

INV:I->O 1 0.562 0.357 q_not00011_INV_0 (q_not0001)

FDE:D 0.197 q

------

Total 1.991ns (1.254ns logic, 0.737ns route)

(63.0% logic, 37.0% route)

======

Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'

Total number of paths / destination ports: 1 / 1

------

Offset: 1.337ns (Levels of Logic = 1)

Source: t (PAD)

Destination: q (FF)

Destination Clock: clk rising

Data Path: t to q

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

------

IBUF:I->O 1 0.824 0.357 t_IBUF (t_IBUF)

FDE:CE 0.156 q

------

Total 1.337ns (0.980ns logic, 0.357ns route)

(73.3% logic, 26.7% route)

======

Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'

Total number of paths / destination ports: 1 / 1

------

Offset: 5.271ns (Levels of Logic = 1)

Source: q (FF)

Destination: q (PAD)

Source Clock: clk rising

Data Path: q to q

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

------

FDE:C->Q 2 0.495 0.380 q (q_OBUF)

OBUF:I->O 4.396 q_OBUF (q)

------

Total 5.271ns (4.891ns logic, 0.380ns route)

(92.8% logic, 7.2% route)

======

Total REAL time to Xst completion: 3.00 secs

Total CPU time to Xst completion: 3.67 secs

-->

Total memory usage is 145748 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 0 ( 0 filtered)

Number of infos : 0 ( 0 filtered)

2.0 3:8 decoder using if else

program:

module decoder(

input [2:0] x,

outputreg [7:0] y

);

always @(x)

begin

if(x==0)

y=1;

else if(x==1)

y=2;

else if(x==2)

y=4;

else if(x==3)

y=8;

else if(x==4)

y=16;

else if(x==5)

y=32;

else if(x==6)

y=64;

else if(x==7)

y=128;

end

endmodule

test bench:

moduletb_decoder;

// Inputs

reg [2:0] x;

// Outputs

wire [7:0] y;

// Instantiate the Unit Under Test (UUT)

decoderuut (

.x(x),

.y(y)

);

initial begin

// Initialize Inputs

x = 0;

// Wait 100 ns for global reset to finish

#100;

x=1;

#100;

x=2;

#100;

x=3;

#100;

x=4;

#100;

x=5;

#100;

x=6;

#100;

x=7;

#100;

// Add stimulus here

end

endmodule

result:

rtl schematic:

technology schematic:

TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT

GENERATED AFTER PLACE-and-ROUTE.

Clock Information:

------

No clock signals found in this design

Asynchronous Control Signals Information:

------

No asynchronous control signals found in this design

Timing Summary:

------

Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: No path found

Maximum output required time after clock: No path found

Maximum combinational path delay: 6.889ns

Timing Detail:

------

All values displayed in nanoseconds (ns)

======

Timing constraint: Default path analysis

Total number of paths / destination ports: 24 / 8

------

Delay: 6.889ns (Levels of Logic = 3)

Source: x<2> (PAD)

Destination: y<7> (PAD)

Data Path: x<2>to y<7>

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

------

IBUF:I->O 8 0.824 0.751 x_2_IBUF (x_2_IBUF)

LUT3:I0->O 1 0.561 0.357 Mdecod_y71 (y_7_OBUF)

OBUF:I->O 4.396 y_7_OBUF (y<7>)

------

Total 6.889ns (5.781ns logic, 1.108ns route)

(83.9% logic, 16.1% route)

======

Total REAL time to Xst completion: 4.00 secs

Total CPU time to Xst completion: 3.67 secs

-->

Total memory usage is 145748 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 0 ( 0 filtered)

Number of infos : 0 ( 0 filtered)

3.0 bit asynchronous counter

program:

moduleasynchronouscount(

inputclk,

outputreg [3:0] q

);

initial q=4'b1111;

always @(negedgeclk)

q[0]=~q[0];

always @(negedge q[0])

q[1]=~q[1];

always @(negedge q[1])

q[2]=~q[2];

always @(negedge q[2])

q[3]=~q[3];

endmodule

test bench

moduletb_async;

// Inputs

regclk;

// Outputs

wire [3:0] q;

// Instantiate the Unit Under Test (UUT)

asynchronouscountuut (

.clk(clk),

.q(q)

);

always #100 clk=~clk;

initial begin

// Initialize Inputs

clk = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

end

endmodule

result:

rtl schematic:

technology schematic:

timing report:

TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT

GENERATED AFTER PLACE-and-ROUTE.

Clock Information:

------

------+------+------+

Clock Signal | Clock buffer(FF name) | Load |

------+------+------+

clk | BUFGP | 1 |

q_0 | NONE(q_1) | 1 |

q_1 | NONE(q_2) | 1 |

q_2 | NONE(q_3) | 1 |

------+------+------+

INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:

------

No asynchronous control signals found in this design

Timing Summary:

------

Speed Grade: -5

Minimum period: 1.381ns (Maximum Frequency: 723.929MHz)

Minimum input arrival time before clock: No path found

Maximum output required time after clock: 5.342ns

Maximum combinational path delay: No path found

Timing Detail:

------

All values displayed in nanoseconds (ns)

======

Timing constraint: Default period analysis for Clock 'clk'

Clock period: 1.381ns (frequency: 723.929MHz)

Total number of paths / destination ports: 1 / 1

------

Delay: 1.381ns (Levels of Logic = 0)

Source: q_0 (FF)

Destination: q_0 (FF)

Source Clock: clk falling

Destination Clock: clk falling

Data Path: q_0 to q_0

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

------

FDR_1:C->Q 3 0.495 0.451 q_0 (q_0)

FDR_1:R 0.435 q_0

------

Total 1.381ns (0.930ns logic, 0.451ns route)

(67.3% logic, 32.7% route)

======

Timing constraint: Default period analysis for Clock 'q_0'

Clock period: 1.381ns (frequency: 723.929MHz)

Total number of paths / destination ports: 1 / 1

------

Delay: 1.381ns (Levels of Logic = 0)

Source: q_1 (FF)

Destination: q_1 (FF)

Source Clock: q_0 falling

Destination Clock: q_0 falling

Data Path: q_1 to q_1

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

------

FDR_1:C->Q 3 0.495 0.451 q_1 (q_1)

FDR_1:R 0.435 q_1

------

Total 1.381ns (0.930ns logic, 0.451ns route)

(67.3% logic, 32.7% route)

======

Timing constraint: Default period analysis for Clock 'q_1'

Clock period: 1.381ns (frequency: 723.929MHz)

Total number of paths / destination ports: 1 / 1

------

Delay: 1.381ns (Levels of Logic = 0)

Source: q_2 (FF)

Destination: q_2 (FF)

Source Clock: q_1 falling

Destination Clock: q_1 falling

Data Path: q_2 to q_2

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

------

FDR_1:C->Q 3 0.495 0.451 q_2 (q_2)

FDR_1:R 0.435 q_2

------

Total 1.381ns (0.930ns logic, 0.451ns route)

(67.3% logic, 32.7% route)

======

Timing constraint: Default period analysis for Clock 'q_2'

Clock period: 1.310ns (frequency: 763.388MHz)

Total number of paths / destination ports: 1 / 1

------

Delay: 1.310ns (Levels of Logic = 0)

Source: q_3 (FF)

Destination: q_3 (FF)

Source Clock: q_2 falling

Destination Clock: q_2 falling

Data Path: q_3 to q_3

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

------

FDR_1:C->Q 2 0.495 0.380 q_3 (q_3)

FDR_1:R 0.435 q_3

------

Total 1.310ns (0.930ns logic, 0.380ns route)

(71.0% logic, 29.0% route)

======

Timing constraint: Default OFFSET OUT AFTER for Clock 'q_2'

Total number of paths / destination ports: 1 / 1

------

Offset: 5.271ns (Levels of Logic = 1)

Source: q_3 (FF)

Destination: q<3> (PAD)

Source Clock: q_2 falling

Data Path: q_3 to q<3>

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)