FPGA Controlled High Performance Amplifier
May06--14
DAC Control Test
Overview:
The DAC Control Test is an automated test that will verify the VHDL code correctly controls the DAC, and that the attenuator and amplifiers in the circuit produce the appropriate corresponding DC offset corrections.
This test will isolate the DAC driver code, and test just its effect on the offset calibration. It will be performed with the FPGA installed on the board. The setup will consist of the board, with its output connected to the GPIB-capable Agilent 34401A Multimeter. The FPGA will be loaded with a special VHDL test fixture that will cycle through each possible DAC output voltage. Each time it sees input on the DC Offset Correction Switch pin, it will cycle to the next output value. For this test, the actual switch will be turned off, and the 6-volt output on the Agilent E3631A will be connected directly to this FPGA input pin. The entire test will be automated using LabVIEW software and GPIB control. The program will trigger each step in output by breifly enabling the 6V output of the power supply. It will then measure and record the resulting amplifier output using the multimeter.
Equipment:
MultimeterAgilent 34401A 6 1/2 Digit Multimeter
Specs:
Power SupplyAgilent E3631A Programmable DC Power Supply
Specs: ftp://ftp.testequity.com/pdf/agtE363xA.pdf
Terms & Definitions:
VHDLHardware description language (code that describes FPGA’s behavior)
DACDigital to Analog Converter
FPGAField Programmable Gate Array – reprogrammable digital logic unit
LabVIEWTest and control automation software
Explanation of Tests:
This test program will begin by measuring and recording the natural DC-offset of the amplifier. Once it has done this, it will trigger the “DC Offset Correction Switch” to tell the FPGA to begin applying offset corrections. It will cycle through each possible DAC output value ranging from 0 to 65535 in intervals of 800 (81 data points) by triggering this same switch. At each of these steps, the program will measure and record the resulting actual DC offset at the output. Each step should represent approximately a .5mV step in offset.
The LabVIEW project and the VHDL test fixture used in this test will be included as a deliverable upon completion of the project. This will ensure that the test can be quickly and easily replicated and maintained.
Diagram:
Test Specifications:
The specifications for this test are two fold:
1)The difference between the natural DC-offset and the resulting range of offsets must at least span the -20mV to +20mV range.
2)Each step in offset voltage must be less than 1mV from the last.