EE141 Fall 1999

Due 11/3/99 5:00pm

Homework #7

Problem 1)

Do problem 7.2 from the book. When specifying Boolean gate delays, use a subscript to annotate the fan-in of the gate. For example, use tand2 and tand4 for the propagation delay of a 2- or 4-input AND gate, as opposed to tand for both.

Problem 2)

Implement a 1-bit static full-adder using the DCVSL logic style (as shown in figure 4.18 of the book) using the minimum number of transistors. Assume that complementary inputs are available. Use no more than 24 transistors.

Problem 3)

The adder in figure 7.9 (page 393 of the book) has an error. Describe why the circuit will not work as shown and give example inputs (Ci0, A0, B0, A1, B1) which cause it to fail.

Problem 4)

Do problem 7.8 from the book. For part c), assume that all inputs switch simultaneously and instantaneously and that complementary inputs are available. Assume that each switch is implemented with an NMOS and a PMOS transistor. Assume that each output is loaded with capacitance Cload. Also assume that all NMOS and PMOS transistors are the same size, which means that your propagation delay expression can be in terms of Ron(n), Ron(p), Cgate, and Cdiff where Cgate and Cdiff are the gate and diffusion region capacitances, which are approximately the same for both transistors.

HINT: Consider a sum broken up into steps as follows (where the first assumed carry is always zero):

bit / 3 / 2 / 1 / 0
A
B / 1
0 / 0
0 / 1
0 / 1
1 / Assumed initial carry
S
C
S
C / 1
0
0
1 / 0
0
1
0 / 1
0
0
1 / 0
1 / 0
1
S
C
S
C / 1
0
1
0 / 0
1 / 0
1 / 0 / 0
1
S
C / 1
0 / 1 / 0 / 0 / 0

Problem 5) (Extra Credit)

a)Propose a modification to the circuit in figure 7.49 (a) (from problem 7.8) which uses the same conditional adder cell (from figure 7.49 (b) ) but requires only 2 switches per stage (except the first stage). Describe how this circuit works.

HINT: Consider a sum broken up into steps as follows (where the first assumed carry is always zero):

bit / 3 / 2 / 1 / 0
A
B / 1
0 / 0
0 / 1
0 / 1
1 / Assumed initial carry
S
C
S
C / 1
0
0
1 / 0
0
1
0 / 1
0
0
1 / 0
1 / 0
1
S
C
S
C / 1
0
0
1 / 0
0
1
0 / 0
1 / 0 / 0
1
S
C
S
C / 1
0
0
1 / 1
0 / 0 / 0 / 0
1
S
C / 1
0 / 1 / 0 / 0 / 0

b)Find an expression for the propagation delay of this adder using the same assumptions as problem 3.

c)For a general N-bit adder, when would this adder be faster than the adder from problem 3?