中 芯 国 际 集 成 电 路 制 造 ( 上 海 ) 有 限 公 司
Semiconductor Manufacturing International (Shanghai) Corp.
Request No. ______
In-house IP Request Form
Version / Date / Revision HistoryV0.0 / yyyy-mm-dd / Initial version
V0.x / yyyy-mm-dd / Revised versions.
V1.0 / yyyy-mm-dd / Fixed version for the IP development
V1.x / yyyy-mm-dd / Contingent version
I. Project Profile ( please refer to the Guideline to fill in this part)
*Project name*Requestor / *Requestor org / Center/division/department
*Account Sales / Must fill for customer driven case / *Account CE / Must fill for customer driven case
*Customer / Must fill for customer driven case / *Customer code / Must fill for customer driven case
*Final deliver date / yyyy-mm-dd / *Application
*Final deliverables / Brief description of the final deliverables (for example, GDS, SDK, CDK, etc)
*Tapeout type / TQV / MPW / New Pilot / Production
Other: ______/ N/A (if tapeout is not needed)
*Tapeout date / Date: YYYY-MM-DD / N/A (if tapeout is not needed)
*Request type / Foundation IP / TQV / IP customization (new design)
IP customization (modification based on the existing IP/design)
For this case, specify the existing IP code ______
*Re-work type / Re-design / Re-characterization / Re-verification by silicon
Re-qualification / N/A (the request is not for the re-work purpose)
Other: ______
*IP type / Stdcell / MEM / I/O / PM
PLL / ADC / DAC / eFuse
NVM / RF / testkeys
Other: ______
*Process type / Logic LL / Logic G / EEPROM / EFlash
CIS / BCD / HV / TSV
Other: ______
*Technology information / **Process features / ___ nm __P __ M __TM Core: __V, IO: __ V
**Design rule version / Provide the ECN or TECN no here
**Spice model version / Provide the ECN or TECN no here, for all the models needed, such as logic model, bit cell model, RF model, HV model, interconnection model etc.
DRC signoff version / Provide the ECN or TECN no here
LVS signoff version / Provide the ECN or TECN no here
Other runsets or utilities
versions (optional) / Provide the versions of other files necessary for the requests, such as the RCX runset, DFM utilities, dummy insertion scripts, and so on
Qual standard (optional)
**Special requirement (If any)
Note : For the IP customization request cases, 1) ** items must be filled; 2) In case the special runset is needed by the customer, please specify them by the item “special requirement (if any)”.
II. Project Scope & Schedule *(please refer to the Guideline to fill in this part)
A. IP customization cases, please use the Appendix, skip B.
B. Foundation and TQV cases
Please specify the specification, deliverables and schedule of the requested IPs one by one here
Please consult DS contact window if other formats will be adopted.
S/N / IP/design requested / Key features, functionality and performance specifications / Final deliverables / Due day /1 / IP1 / Key feature 1
…
Key feature n
Key function 1
…
Key function n
Key spec 1
…
Key spec n
(Use datasheet or attachment if needed) / Deliverable 1 / Due day 1
Deliverable 2 / Due day 2
… / …
Deliverable n / Due day n
2 / IP2
…
N / IPn
III. Business Justification and Wafer Forecast * (pls refer to the Guideline to fill in this part)
1. Wafer forecast (*must for the customer-driven cases)wafer volume > xxx K wafers/month since YYYY/MM
2. Business Justification (*please send separate email to DS contact window if the information is confidential)
Signatures
Requestor / Requestor’s manager(Department or above)
Guideline
I. Project Profile
(Guidelines and notes to fill in the project profile:
1. All the * items must be filled
2. The item “Final deliverables” only needs a brief description. The details of “Final deliverables” will be
elaborated in the section of Project Scope & Schedule.
3. The item “Tapeout type” and “Tapeout date” are for the tapeouts of requestor’s project
4. The item “Re-work” is only for those re-work cases. Please fill in N/A if no re-work involved.
5. The items for “Technology information”:
- Define FDK as the total package of the technology related documents, mainly including DR, PCM,
spice model, DRC/LVS/RCX/TF runset, PDK, DFM utilities, dummy insertion utilities, et al.
- By default, the IP deliverables will be based on the latest versions of FDK. If there is FDK version
change before the final deliver date in this form, it’s the mutual responsibility of the requestor and DS
to decide how to revise the project schedule or/and scope if the revision is needed.
- For the IP customization cases, the process feature and FDK versions must be specified, in
particular when the FDK version is different from the standard offerings of the baseline process
- Please fill in N/A if no special requirement for the optional items
6. Please change the security setting of your system to allow the embedded Marco in the table running.
Then, you can double click the option boxes and make your choices conveniently.
7. Please consult DS contact window if any question.)
II. Project Scope & Schedule *
(Guidelines and notes to describe the project scope:
1. For each IP, please clearly specify the following items in order to reduce the communication iterations:
a). IP key features and functionality specification (must)
b). IP key performance specification for speed, power, size, architecture, etc (must)
c). Final deliverables (must)
d). Intermediate deliverables (optional)
e). Due day of each final deliverables (must)
2. For the IP customization request cases, strongly recommend following the templates in the Appendix.
Please remove the unnecessary contents of the Appendix to make this form more concise.
3. For the foundation IP and TQV requests, recommend using the table below to describe the scope
and schedule. If other formats will be adopted, please remove the table below.
4. If necessary, please use the attachments like SoW or datasheet to describe the IP specs.
5. Please consult DS contact window if any question.)
III. Business Justification and Wafer Forecast *
(Guidelines and notes to describe the biz justification and wafer forecast:
1. The following outlines can be used to address the justifications for your request case:
a). Corporate-level decision
b). Contributions to the business development or/and revenue growth
c). Contributions to the funding raising or/and other financial operation
d). Contributions to the technology development or/and qualification
e). Other supporting factors to justify the request case
2. The wafer forecast must be provided for the customer-driven cases.
Example for wafer forecast: wafer volume > xxx K wafers/month since YYYY/MM:
3. Please attach the related meeting minutes if there was already a conclusion
4. Please send another emails if the business or financial information is confidential. )
Appendix
You can refer to the following content to specify your requests in details.
Please remove the following pages if you won’t include them in your request.
(A) System Description
I. Product General Function Description (preferred)
II. Full IP List used or planned to be used in the project*
Item# / SMIC In-house IP/Library Name / IP/Library Brief DescriptionItem# / SMIC Third Party IP/Library Name / IP/Library Brief Description
III. System Block Diagram (preferred)
(B) Standard Cell Library
Needed date / YYYY-MM-DDReference Library Name (if any) / Version
Design Kit Requirement / Document
Netlist
GDS
Verilog Model
LEF
Apollo P&R
Synopsys synthesis library
Synopsys symbol library
Mentor ATPG library
Library Category / Regular VT
High VT
High Performance
High Speed
High Density
Core Voltage Supply / Single Voltage / 1.2V for 90nm LL
1.0V for 90nm G
Multiple Voltage / High Level 1.2V, Low Level 1.0V for 90nm LL
High Level 1.0V, Low Level 0.8V for 90nm G
Power Consumption
Chip Frequency
Design Application
Other Requirements
(C) Memory Instance
Needed date / YYYY-MM-DDSingle Port SRAM
Configuration
(Word x Bits) / Dynamic Power
(mA) / Standby Power
(uA) / Area
(mm2) / Frequency
(MHz) / Write Mask
(WEN Width) / Redundancy
Yes No
Yes No
Dual Port SRAM
Configuration
(Word x Bits) / Dynamic Power
(mA) / Standby Power
(uA) / Area
(mm2) / Frequency
(MHz) / Write Mask
(WEN Width) / Redundancy
Yes No
Yes No
Single Port Register File
Configuration
(Word x Bits) / Dynamic Power
(mA) / Standby Power
(uA) / Area
(mm2) / Frequency
(MHz) / Write Mask
(WEN Width) / Redundancy
Yes No
Yes No
Two Port Register File
Configuration
(Word x Bits) / Dynamic Power
(mA) / Standby Power
(uA) / Area
(mm2) / Frequency
(MHz) / Write Mask
(WEN Width) / Redundancy
Yes No
Yes No
ROM
Configuration
(Word x Bits) / Dynamic Power
(mA) / Standby Power
(uA) / Area
(mm2) / Frequency
(MHz) / Write Mask
(WEN Width) / Others
Other Requirements
(D) IO Library
Needed date / YYYY-MM-DDReference IO Name (if any) / Version
Design Kit Requirements / Document
Verilog Model
LEF
Design data for Apollo P&R
Synopsys synthesis library
GDS (for Standard IO only)
Netlist (for Standard IO only)
Other requirements ______
Specification Requirements / Specification compatible with ______IO library
ESD / HBM mode _____KV
MM mode _____V
Customization Characteristic with Function Block and Truth Table
Other Requirements
(E) PLL
Needed date / YYYY-MM-DDReference IP Name (if any) / Version
Input Frequency Range
Output Frequency Range
Jitter
Power Consumption (Normal)
Power Consumption (Standby)
Other Requirements
(F) ADC
Needed date / YYYY-MM-DDReference IP Name (if any) / Version
Characteristics / Min / Typ / Max / Unit / Remarks
Resolution / Bit
Conversion Rate / Hz
Number of Channels / CH
Analog Power / V
Digital Power / V
Input Mode / Single-ended
Differential
Selectable
Input Common Mode / V
Input Range / mV
Input Frequency / MHz
THD / dB
SFDR / dB
DNL / LSBs
INL / LSBs
SINAD / dB
ENOB / Bit
Input DC Offset / mV
Conversion Latency / cycle
Power Dissipation / mW
Layout Area / mm2
Clock Duty Cycle / %
Other Requirements
(G) DAC
Needed date / YYYY-MM-DDReference IP Name (if any) / Version
Resolution
Application Frequency
INL
DNL
Power Supply
Output Range
Single End / Differential Output
Other Requirements
(H) Voltage Regulator
Needed date / YYYY-MM-DDReference IP Name (if any) / Version
Maximum voltage of external power supply / V
Minimum voltage of external power supply / V
Output Voltage / V
Loading Current / mA
Quiescent Current / uA
Standby Current / uA
Ripple Requirement / mV
Power Level of the Control Signal (Such as PD) / V
Number of Pins for Input Power
Number of Pins for Output Power
External Capacitor Allowed / Yes No
Loaded Parts / Logic
Mixed Signal
RF
Memory
Other Requirements
(I) EEPROM
Needed date / YYYY-MM-DDReference IP Name (if any) / Version
Memory Type / EEPROM
OTP ROM
MASK ROM
Number of Words / Word
Number of Bits / Bit
Power Supply / V
Acceptable Active Current (Max.) / mA
Acceptable Standby Current (Max.) / uA
Acceptable Read Access Time (Max.) / ns
Operating Frequency / MHz
Other Requirements
(J) EFUSE
Needed date / YYYY-MM-DDReference IP Name (if any) / Version
Total Number of bits / bit
Read data bus width / bit
Min / Typ / Max
Core Power Supply / V
IO Power Supply / V
Programming Voltage (VPP) / V
Acceptable Read Access Time (Max.) / nS
Acceptable Current for reading (Max) / mA
Acceptable Standby Current (Max.) / uA
Other Requirements
(K) Other IP
Needed date / YYYY-MM-DDReference IP Name (if any) / Version
Detail Description
SMIC Confidential [Version: 2012-Dec-22]
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