DOC/LP/01/28.01.09

/ LESSON PLAN / LP: CS6201
LP Rev. No: 00
Date: 17- 01-2014
Page 6 of 6
CS6201 - DIGITAL PRINCIPLES AND SYSTEM DESIGN
Unit : 6 Branch : IT Semester : II

UNIT-I BOOLEAN ALGEBRA AND LOGIC GATES 9

Syllabus: Review of Number Systems – Arithmetic Operations – Binary Codes – Boolean Algebra and Theorems – Boolean Functions – Simplification of Boolean Functions using Karnaugh Map and Tabulation Methods – Logic Gates – NAND and NOR Implementations.

Objective: To understand different methods used for the simplification of Boolean functions

Session
No / Topics to be covered / Time / Ref / Teaching Method
1. / Review of Number Systems, Binary Codes / 50 min / 1 / BB
2. / Arithmetic Operations / 50 min / 1 / BB
3. / Boolean Algebra and Theorems / 50 min / 1 / BB
4. / Boolean Functions / 50 min / 1 / BB
5. / Simplification of Boolean Functions using Karnaugh Map / 50 min / 1 / BB
6. / Simplification of Boolean Functions using Karnaugh Map / 50 min / 1 / BB
7. / Simplification of Boolean Functions using Tabulation Methods / 50 min / 1 / BB
8. / Simplification of Boolean Functions using Tabulation Methods / 50 min / 1 / BB
9. / Logic Gates – NAND and NOR Implementations / 50 min / 1 / BB
10. / Boolean Functions – NAND and NOR Implementations / 50 min / 1 / BB
11. / Review of Unit-1 / 50 min / 1 / BB

UNIT II COMBINATIONAL LOGIC 9

Syllabus: Combinational Circuits – Analysis and Design Procedures – Circuits for Arithmetic Operations, Code Conversion – Decoders and Encoders – Multiplexers and De multiplexers – Introduction to HDL – HDL Models of Combinational circuits.

Objective: To design and implement a system that uses combinational logic for the given specification; Simulate combinational logic systems using verilog or VHDL.

Session
No / Topics to be covered / Time / Ref / Teaching Method
12. / Combinational Logic Introduction / 50 min / 1 / BB
13. / Combinational Circuits - Analysis and Design Procedures / 50 min / 1 / BB
14. / Circuits for Arithmetic Operations / 50 min / 1 / BB
15. / Circuits for Arithmetic Operations / 50 min / 1 / BB
16. / Code Conversion / 50 min / 1 / BB
17. / Decoders and Encoders / 50 min / 1 / BB
18. / Multiplexers / 50 min / 1 / BB
19. / De multiplexers / 50 min / 1 / BB
20. / Introduction to HDL / 50 min / 1 / BB
21. / HDL Models of Combinational circuits / 50 min / 1 / BB
22. / HDL Models of Combinational circuits / 50 min / 1 / BB

UNIT III SYNCHRONOUS SEQUENTIAL LOGIC 9

Syllabus: Sequential Circuits – Latches and Flip Flops – Analysis and Design Procedures – State Reduction and State Assignment – Shift Registers – Counters – HDL for Sequential Logic Circuits.

Objective: To design and implement synchronous sequential system for the given specification; Simulate sequential logic systems using verilog or VHDL.

Session
No / Topics to be covered / Time / Ref / Teaching Method
23.  / Sequential Circuits - Introduction / 50 min / 1 / BB
24.  / Latches and Flip Flops / 50 min / 1 / BB
25.  / Sequential Circuits-Analysis and Design Procedure / 50 min / 1 / BB & OHP
26.  / State Reduction and State Assignment / 50 min / 1 / BB & OHP
27.  / State Reduction and State Assignment / 50 min / 1 / BB & OHP
28.  / Shift Registers / 50 min / 1 / BB & OHP
29.  / Counters / 50 min / 1 / BB & OHP
30.  / Counters / 50 min / 1 / BB & OHP
31.  / HDL for Sequential Logic Circuits / 50 min / 1 / BB & OHP
32.  / HDL for Sequential Logic Circuits / 50 min / 1 / BB & OHP
33.  / Review of Unit-2 and 3 / 50 min / 1 / BB & OHP

UNIT IV ASYNCHRONOUS SEQUENTIAL LOGIC 9

Syllabus: Analysis and Design of Asynchronous Sequential Circuits – Reduction of State and Flow Tables – Race-free State Assignment – Hazards.

Objective: To design and implement Asynchronous sequential system for the given specification.

Session
No / Topics to be covered / Time / Ref / Teaching Method
34.  / Asynchronous Sequential Circuits-Introduction / 50 min / 1 / BB & OHP
35.  / Analysis and Design of Asynchronous Sequential Circuits / 50 min / 1 / BB & OHP
36.  / Analysis and Design of Asynchronous Sequential Circuits / 50 min / 1 / BB & OHP
37.  / Reduction of State and Flow Tables / 50 min / 1 / BB & OHP
38.  / Reduction of State and Flow Tables / 50 min / 1 / BB & OHP
39.  / Race-free State Assignment / 50 min / 1 / BB & OHP
40.  / Race-free State Assignment / 50 min / 1 / BB & OHP
41.  / Hazards / 50 min / 1 / BB & OHP
42.  / Hazards / 50 min / 1 / BB & OHP
43.  / Review of Unit-4 / 50 min / BB

UNIT V MEMORY AND PROGRAMMABLE LOGIC 9

Syllabus: RAM and ROM – Memory Decoding – Error Detection and Correction – Programmable Logic Array – Programmable Array Logic – Sequential Programmable Devices – Application Specific Integrated Circuits.

Objective: To design and implement memory accessing systems and systems using PLA, PAL.

Session
No / Topics to be covered / Time / Ref / Teaching Method
44.  / Memory and Programmable logic Introduction / 50 min / 2 / BB
45.  / RAM and ROM – Memory Decoding / 50 min / 2 / BB
46.  / Error Detection and Correction / 50 min / 2 / BB
47.  / Programmable Logic Array / 50 min / 2 / BB
48.  / Programmable Array Logic / 50 min / 2 / BB
49.  / Sequential Programmable Devices / 50 min / 2 / BB
50.  / Application Specific Integrated Circuits / 50 min / 2 / BB
51.  / Tutorial / 50 min / 2 / BB
52.  / Review of Unit-5 / 50 min

COURSE DELIVERY PLAN

Week / 1 / 2 / 3 / 4 / 5 / 6 / 7 / 8 / 9 / 10 / 11 / 12 / 13 / 14
I / II / I / II / I / II / I / II / I / II / I / II / I / II / I / II / I / II / I / II / I / II / I / II / I / II / I
Units / 1 / 1 / 1 / 1 / 1 / 1
2 / 2 / 2 / 2 / 2 / 2 / 2 / 3 / 3 / 3 / 3 / 3 / 3
4 / 4 / 4 / 4 / 4 / 5 / 5 / 5 / 5 / 5

TEXT BOOKS

1. Morris Mano M. and Michael D. Ciletti, “Digital Design”, IV Edition, Pearson Education, 2008

REFERENCES

2. John F. Wakerly, “Digital Design Principles and Practices”, Fourth Edition, Pearson Education, 2007

3. Charles H. Roth Jr, “Fundamentals of Logic Design”, Fifth Edition – Jaico Publishing House, Mumbai, 2003.

4. Donald D. Givone, “Digital Principles and Design”, Tata Mcgraw Hill, 2003.

5. Kharate G. K., “Digital Electronics”, Oxford University Press, 2010.

Prepared by / Approved by
Signature
Name /
Designation / V.Rajaram/Assistant Professor-IT / Dr. D. Balasubramanian/HOD-IT
Date / 17/01/2014