EE4311 Design of VLSI

Homework 2

In this homework, you will design a few commonly used gates and study the effects of load capacitance and transistor dimensions on gate speed. We will again use the 0.25μm technology.

Several important notes:

  • When you simulate the designed gate, please give the input signal source in the order of either ns or psso that you can easily recognize the delay in the output waveform.
  • As you know from HW1, there are two options of circuit views that can be simulated, the schematic view and extracted view, with the later more realistic (having parasitic capacitances). For this homework, we will useschematic view for simulation (to reduce your workload).
  • For some very large transistors, you may want to use multiple finger structures. And if you do that, Cadence will report each finger as a single transistor in LVS, note that this is not an error. For example, you have 6 transistors in your 3-input NAND gate, if each transistor is implemented using 4 fingers in the layout, the LVS will show 4*6=24 active devices for the extracted layout compared to 6 active devices in the layout (which is not an error).
  • When you add VDD and GND, please make sure to select these two components from analogLib, not other libraries.

1. Study the effect of sizing in an inverter chain on the total delay. The first inverter should be a minimum-size inverter (say, 9λ/2λ for PMOS and 3λ/2λ for NMOS). Then find the delay of inverter chain for the following cases illustrated below:

(note: to consider the above four cases, you would need to first estimate what would be the unit input capacitance for the first stage which is a minimum-size inverter? Use Cin=Wn*Ln*Cox + Wp*Lp*Cox to estimate it and the load capacitance at the last stage should be 64×Cin. Take Cox=6fF/μm2)

2.Three-input NAND gate design.

(2a) Implement a 3-input NAND gate in schematic editor.

(2b) Attach a 500fF capacitor to the output of the NAND gate, and then size your NAND gate so that the worst-case L-H and H-L delay should be roughly equal to those of a minimum-size inverter (by just using the equivalent resistance method discussed in class). Simulate the schematic view to record worst-case L-H and H-L delay.

(2c) Attach a 500fF capacitor to the output of the NAND gate you designed. Measure the L-H delay for all possible cases (For this measurement, set the transition time, also the rise time and fall time,of input signal sources to 10ps). Make a table and submit the table.

(2d Optional with a bonus of 2pts if completed correctly) Draw the layoutfor the schematic design from (2b), but try to minimize the area of the layout. For this, you need to follow closely the design rule and use the minimum distance or width whenever possible. After you get the layout, use the ruler to measure the width and length of your layout (you can invoke the ruler by press the key ‘k’). Please submit the prints of the gate layout with ruler measurements and correct DRC and LVS match.

3.With the three-input NAND gate designed above, now attach a 100fF load capacitor at the output of the NANDgate. Keep the lengths of the transistor constant at 0.3um, and modify the widths such that the worst caseL-to-H and H-to-L delay become 0.3ns. Now increase the load capacitor to 1000fF in steps of 300fF andin each case please modify the transistor widths such that the L-to-H and H-to-Ldelay remain to be 0.3ns when measured in schematic simulation. Draw the graph with the capacitance in the x-axis, and Wn/Ln and Wp/Lp on the y-axis. Submit the graph. How is the W/L ratio changing with load capacitor?(Note: set the rise/fall time of input signal pulse to 10ps)

Comments:

After this lab, you should be able to summarize some empirical rules regarding sizing of the basic gates for delay. You do not have to include them in your report, but use them for your future more complex design.