EE/CEG 459 - Integrated Circuit Design Synthesis

EE/CEG 459 - Integrated Circuit Design Synthesis

with VHDL

1997-1999 EE 459-4. Integrated Circuit Design Synthesis with VHDL (co-listed with

Catalog Data CEG 459). Application of VHSIC hardware description language (VHDL) to the design, analysis, multilevel simulation and synthesis of digital integrated circuits. A commercial set of CAD tools (Mentor Graphics) will be used in the laboratory portion of the course. Prerequisites: CEG 220, C programming or equivalent and EE/CEG 260.

Textbook Perry, VHDL, McGraw-Hill, 1994.

Additional 1. Roth, Digital Systems Design Using VHDL, PWS, 1998

References 2. Dewey, Analysis and Design of Digital Systems with VHDL, PWS, 1997

Coordinator Mike Bakan, Adjunct Instructor of Electrical Engineering

Khalid Abed, Visiting Assistant Professor of Electrical Engineering

Course Objective This course will provide each student with the background needed to design, develop, and test digital circuits using the IEEE standard VHSIC hardware description language (VHDL). Emphasis is placed on top-down design methodology beginning with purely behavioral descriptions which are then decomposed to gate-level structural descriptions. The process of this evolution will be studied from both the manual as well as synthesized approached. Laboratory experience will allow each student to design and verify a variety of designs ranging from simple to complex.

Topical Each student should

Prerequisites ¨ understand the theory of digital and logic circuits

¨ know combinatorial logic design principles, tools and techniques

¨ know the concepts of sequential logic familiarity

¨ be able to program in “C” language

Learning For each student to

Objectives ¨ know the set of data types used in VHDL programming

¨ understand the concepts of behavioral modeling and sequential processing as applied to basic gates and digital and logic circuits

¨ know the set of VHDL subprograms, packages and resolution functions

¨ understand predefined attributes and resolution functions

¨ understand the concepts of design synthesis

¨ be able to apply the principle of test bench design

¨ be able to synthesize digital integrated circuits

Computer Each student will use Mentor Graphics and VHDL software on Sun Sparc work-

Laboratory stations to do the design analysis, multilevel simulation and synthesis of digital integrated circuits.

Estimated ABET Engineering Science: 2 credits or 50%

Category Content Engineering Design: 2 credits or 50%

091201