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Job Listings

ASIC Mixed Signal Engineer-TEK006874 (Santa Clara, CA, USA)

Job Responsibilities

The ASIC Mixed Signal engineer will be a member of the ASIC team that interacts with Analog/circuit designers, digital/RTL designers, PD and verification teams. Will be responsible for Hard Custom Macro development and CAD to support the following activities under guidance of senior team members:

  • Working with internal and external teams to develop custom behavioral Verilog/verilogAand .lib models for custom macro
  • Development AMS simulation environment at block and chip level
  • Development automated verification environment in Verilog for custom macro
  • Development verification environment in AMS
  • Developing timing checks and .lib for the analog and custom interface blocks
  • Working with Physical design team on integration of custom IP
  • Working with analog and digital team on extraction, timing validation and performance simulation

Job Requirements
Essential Requirements
  • M.S./PhD in Electrical or Computer Engineering
  • Strong Academic references and GPA > 3.5/4.0
  • Academic background in circuit Theory
  • Academic background in IC development
  • Demonstrated analytic and problem solving skills
  • Demonstrated ability to work in large multi-site teams
  • Strong written/verbal communication skills
  • Experience in Spectre, AMS, Verilog, including C/C++
  • Experience with algorithm modeling and simulation in MATLAB/Simulink
Preferred Requirements
  • Internship/industry experience in circuit and ASIC
  • Exposure to analog and mixed-signal IC design
  • Familiarity with standard interfaces (DDR, PCI, SPI,etc)
  • Academic backgrounds in the following areas: Low geometry CMOS, Digital circuits, DLL, ADC, DAC, PLL, Opamp, comparators etc.
  • Knowledge and applied use of Verilog or VHDL and verificationtools/methodology (including SystemVerilog and OVM)
  • Experience of modeling HW using C++/SystemC and HW/SW co-simulation techniques is a plus

ASIC Mixed Signal Engineer-TEK006869(Santa Clara, CA, USA)
Job Responsibilities
The ASIC Mixed Signal engineer will be a member of the ASIC team in Santa Clara that interacts with Analog/circuit designers, digital/RTL designers, PD and verification teams Will be responsible for Hard Custom Macro development to support the following activities under guidance of senior team members:
  • Working with internal and external teams to develop custom behavioral Verilog/Verilog-A and .lib models for custom macro
  • SAR ADC design, floor plan and layout
  • Development AMS simulation environment at block and chip level
  • Development automated verification environment in Verilog for custom macro
  • Development verification environment in AMS
  • Developing timing checks and .lib for the analog and custom interface blocks
  • Working with Physical design team on integration of custom IP
  • Working with analog and digital team on extraction, timing validation and performance simulation
Job Requirements
  • The successful candidate will possess the following combination of education and experience:
  • PhD or Master’s degree with a minimum of 2+ years’ experience in sub-micron CMOS process technologies. Circuit design experience of high performance analog products (High speed SAR ADCs)
  • Experience with design of broadband, low noise and high linearity blocks.
  • SAR Async design.
  • Proficient in Cadence design tools, MATLAB and Linux environment.
  • Expert in fundamental of high-speed circuit design for low power.
  • To have a methodological approach to design process and follow company methodology and documentation requirements.
  • Experience in EM simulation is a plus.
  • Lab verification and test engineering support.
  • Able to work in multi-disciplinary team environment and provide feedback.
  • Strong communication, presentation and documentation skills.
  • Experience in AMS, Verilog and Verilog A

Please contact Alex Chang ()

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