Award Software
Chipset Features Setup
This section allows you to configure the system based on the specific features of the installed chipset. This chipset manages bus speeds and access to system memory resources, such as DRAM and the external cache.
Auto Configuration
If enabled, Auto Configuration allows the BIOS to select a standard, optimal configuration. When disabled, it reverts to the setup information read from the CMOS.
Read CAS Pulse Width
This determines duration of the Column Address Strobe pulse during DRAM refresh. The unit of measure is a CPU cycle.
2T / Two cycles (Default)3T / Three cycles
4T / Four cycles
DRAM Write CAS Width
This determines the duration of the Column Addres Strobe durning writes to DRAM. As above, the unit of measure is a CPU cycle.
3T / Three cycles (Default)2T / Two cycles
L1 Cache Update Mode
This allows you to set the write policy for the CPU’s internal cache. The options for this feature are Write-Back and Write-Through. Write-Through means that memory is updated with data held in the cache whenever the CPU issues a write cycle. On the other hand, Write-Back causes memory to be updated only under certain conditions such as read requests to the memory whose contents are currently in the cache. Write-Back allows the CPU to operate with fewer interruptions, increasing its efficiency.
WB / Write Back enabled (Default)WT / Write Back disabled
L2 Cache Update Mode
This allows you to set the write policy for the CPU’s external cache. The options for this feature are Write-Back and Write-Through. Write-Through means that memory is updated with data held in the cache whenever the CPU issues a write cycle. On the other hand, Write-Back causes memory to be updated only under certain conditions such as read requests to the memory whose contents are currently in the cache. Write-Back allows the CPU to operate with fewer interruptions, increasing its efficiency.
WB / Write Back enabledWT / Write Back disabled (Default)
L2 (WB) Tag Bit Length
Cache tag bits are used to report the status of the data held in the cache. This item allows you to select the number of bits used to report the status.
8 Bits / Eight tag bits (Default)7 Bits / Seven tag bits.
SRAM Speed Option
This allows you to configure the speed of the external, L2 cache. It is very unlikely that you would need to select any speed slower than the default, Fastest, setting. The only time any change might be required would be if the performance of the SRAM chips is below the speed required by the CPU. In such a case, a slower speed would be required to maintain the integrity of the data held in the cache.
Fastest / Maximum DRAM speed (Default)Slowest / Minimum DRAM speed
Slower / Slower than an average DRAM speed
Faster / Faster than an average DRAM speed
SRAM Burst R/W Cycle
This sets the timing of SRAM read and write cycles in CPU cycles.
1T / One cycle (Default)2T / Two cycles
3T / Three cycles
Burst SRAM Burst Cycle
This sets the precise timing of the burst mode read and write cycles to and from the external cache.
4-1-1-1 / Slower3-1-1-1 / Fastest (Default)
Refresh RAS Active Time
This allows you to select the time duration in which Row Address Strobe DRAM refresh is active.
6T / Six CPU cycles (Default)5T / Five CPU cycels
DRAM RAS to CAS Delay
Row Address Strobe and Column Address Strobe are both used when DRAM is written to, read from or refreshed. This setting determines the precise timing between the two address strobes.
4T / Four CPU cycles (Default)3T / Three CPU cycles
DRAM RAS Precharge Time
Defines the length of time for Row Address Strobe is allowed to precharge.
4T / Four CPU cycles (Default)5T / Five CPU cycles
Gate A20 Emulation
The chipset supports a fast Gate A20 emulation mode. Traditionally, the Gate A20 was handled by the keyboard controller, but this chipset supports a much faster version.
Enabled / Fast Gate A20 enabled (Default)Disabled / Gate A20 handled by the slower keyboard controller
Fast Reset Emulation
When enabled, this setting allows the BIOS to re-boot your system without having to re-initialize all of your hardware. This allows for a faster re-boot.
Enabled / Fast reset emulation used (Default)Disabled / Conventional re-boot employed.
Slow Refresh (1:4)
A final setting for DRAM refresh allows CAS to take place without using a CPU cycle. This is ofter referred to as “hidden” CAS. Fast refresh is the default.
Disabled / Using fast refresh (Default)Enabled / Using slow refresh
System BIOS Cacheable
As with caching the Video BIOS above, enabling this selection allows accesses to the system BIOS ROM addressed at F0000H-FFFFFH to be cached.
Enabled / BIOS access cachedDisabled / BIOS access not cached (Default)
Video BIOS Cacheable
When enabled, the Video BIOS cache will cause access to video BIOS addressed at C0000H to C7FFFH to be cached.
Enabled / Video BIOS access cachedDisabled / Video BIOS access not cached (Default)
Latency from ADS# status
This allows you to configure how long the CPU waits for the Address Data Status (ADS). In general practice, this should not need to be changed from the default. However, should you add a faster CPU to your system, you may find it necessary to increase the latency (delay).
3T / Three CPU clocks2T / Two CPU clocks (Default)
Refresh When CPU Hold
When enabled, this causes the CPU to hold, or pause, while DRAM refresh is taking place.
Enabled / CPU waits during DRAM refreshDisabled / DRAM refresh does not hold CPU (Default)
Snoop Filter
When enabled, cache snoop filters are implemented which ensure the data integrity (cache coherency) while reducing the snoop frequency to a minimum.
Enabled / Snoop filtering used to check the cacheDisabled / Snoop filtering not used (Default)
Post Write CAS Active
Sets the lenght of time, in CPU cycles, during which Column Address Strobe remains active after a write is completed.
1T / One CPU cycle (Default)2T / Two CPU cycles.
CPU/PCI Post Write Delay
Sets the length of time, in CPU cycles, during which CPU to PCI posted writes are delayed.
1T / One CPU cycle (Default)2T / Two CPU cycles.
PCI Clock Frequency
This allows you to configure the clock rate for the PCI bus. Theoretically, the PCI bus can operate at speeds from 0 Mhz to 33 Mhz. Most frequencies are measured in terms of the CPU clock speed. For example, if the CPU operates at 33 Mhz, a setting of CPUCLK/3 would mean that the PCI bus was operating at 11 Mhz (33/3 = 11).
CPUCLK/1.5 / CPU speed / 1.5 (Default)CPUCLK/3 / CPU speed / 3
14 Mhz / 14 Mega Hertz
CPUCLK/2 / CPU speed / 2
Max, Burstable Range
This sets the size of the maximum range of contiguous memory which can be addressed by a burst from the PCI bus.
0.5Kb / One half kilobyte (Default)1Kb / One kilobyte
CPU/PCI Burst Mem. Write
When enabled, the system will support burst writes to memory from both the CPU and PCI.
Enabled / Burst writes to memory supported by both the CPU and the PCI bus.Disabled / Burst writes to memory not supported. (Default)
CPU/PCI Post Mem. Write
When enabled, a fast buffer will be used for posting writes to memory. Using the fast buffer allows the CPU to not have to wait for the completion of the write cycle to slow DRAM.
Enabled / Writes posted in a fast buffer.Disabled / Memory writes not posted in a fast buffer. (Default)
ISA Bus Clock Frequency
This allows you to set the speed at which the standard ISA bus operates. Two of the settings are speeds which are fractions of the operating speed of the PCI bus. If the PCI bus is operating at its theoretical maximum, 33 Mhz., a setting of PCICLK/3 would yield an ISA speed of 11 Mhz. Since the standard ISA AT-bus has a defined maximum speed of approximately 8 Mhz., many ISA devices have been designed for this speed. While you may be able to operate most devices as higher ISA bus speeds, nevertheless, you may encounter a device which will not function properly.
7.159 Mhz / (Default)PCICLK/4 / One fourth the speed of the PCI bus.
PCICLK/3 / One third the speed of the PCI bus.
Non_Cacheable Block 1
This allows you to set aside a area of adapter ROM which cannot be cached during reads and/or writes. When enabled, you can then determine the starting address and size of the block.
Award BIOS 4.5 Setup UtilityChipset Features Setup § Page 1
Award Software
Power Management Setup
The Power Management Setup allows you to configure you system to most effectively save energy while operating in a manner consistent with your own style of computer use.
Power Management
This category allows you to select the type (or degree) of power saving and is directly related to the following modes:
1.HDD Power Down
2.Doze Mode
3.Standby Mode
4.Suspend Mode
There are four selections for Power Management, three of which have fixed mode settings.
Disable (default) / No power management. Disables all four modesMin. Power Saving / Minimum power management. Doze Mode = 1 hr. Standby Mode = 1 hr., Suspend Mode = 1 hr., and HDD Power Down = 15 min.
Max. Power Saving / Maximum power management -- ONLY AVAILABLE FOR SL CPU’S. Doze Mode = 1 min., Standby Mode = 1 min., Suspend Mode = 1 min., and HDD Power Down = 1 min.
User Defined / Allows you to set each mode individually. When not disabled, each of the ranges are from 1 min. to 1 hr. except for HDD Power Down which ranges from 1 min. to 15 min. and disable.
PM Control APM
When enabled, an Advanced Power Management device will be activated to enhance the Max. Power Saving mode and stop the CPU internal clock.
If the Max. Power Saving is not enabled, this will be preset to No.
Video Off Option
When enabled, this feature allows the VGA adapter to operate in a power saving mode.
Always On / Monitor will remain on during power saving modes.Suspend --> Off / Monitor blanked when the systems enters the Suspend mode.
Susp,Stby --> Off / Monitor blanked when the system enters either Suspend or Standby modes.
All Modes --> Off / Monitor blanked when the system enters any power saving mode.
Video Off Method
This determines the manner in which the monitor is blanked.
V/H SYNC+Blank / This selection will cause the system to turn off the vertical and horizontal synchronization ports and write blanks to the video buffer.Blank Screen / This option only writes blanks to the video buffer.
Suspend Switch
This allows you to choose whether or not your system will go into a complete Suspend mode.
Enabled / System allowed to go into Suspend modeDisabled / System will not go into Suspend mode
Doze Speed (div by)
Sets the CPU’s speed during Doze mode. The speed is reduced to a fraction of the CPU’s normal speed. The divisors range from 1 to 1/8th, 1/2 is the default.
Stdby Speed (div by)
Sets the CPU’s speed during Doze mode. The speed is reduced to a fraction of the CPU’s normal speed. The divisors range from 1 to 1/8th, 1/3 is the default.
PM Timers
The following four modes are Green PC power saving functions which are only user configurable when User Defined Power Management has been selected. See above for available selections.
HDD Power Down
Allows you to set the time delay before the hard disk drive is powered-down. The default setting of Disable means that the hard drive always remains in a ready state.
Disable / Hard drive always remains ready1-15 minutes / Choices for when the drive is powered-down
Suspend / Drive powered-down when the system goes into the Suspend mode.
Doze Mode
When enabled and after the set time of system inactivity, the CPU clock will run at at slower speed while all other devices still operate at full speed.
Standby Mode
When enabled and after the set time of system inactivity, the fixed disk drive and the video would be shut off while all other devices still operate at full speed.
Suspend Mode
When enabled and after the set time of system inactivity, all devices except the CPU will be shut off.
PM Events
Even though the system may be in a power saving mode, some devices can be used (accessed) without waking up the system. An example would be to receive a fax through a serial port and print it through the LPT printer port while the system is in a “sleep” mode. Similiarly, device activity will not prevent the system from going into a power saving (sleep) mode.
The following entries allow the user to determine which devices are to be available. Settings are either Enable or Disable. Enable is the default of most except the Real Time Clock (IRQ 8) and the VGA. Enable means that activity will prevent the system from entering a Power Management mode or activity will wake the system up.
COM Ports Activity
Selecting Disable allows you to use the serial ports, COM 1, COM 2, COM 3 and COM 4, without causing the system to enter or leave a “sleep” mode.
LPT Ports Activity
Selecting Disable means that it is possible to print while the system is in “sleep” mode.
HDD Ports Activity
Selecting Disable means that disk drive activity will not prevent the system from going into “sleep” mode or “awaken” it.
PCI/ISA Master Act
When enabled, PCI or ISA bus activity will wake the system up.
IRQ1-15 Activity
When enable, any IRQ activity will cause the system to wake up. This contrasts with the individual IRQ settings below.
VGA Activity
This refers to any video controller activity. As usual, when Disabled, video activity will not wake or prevent the system from going to “sleep”.
The following is a list of IRQ’s, Interrupt ReQuests, which can be exempted much as the COM ports and LPT ports above can. When an I/O device wants to gain the attention of the operating system, it signals this by causing an IRQ to occur. When the operating system is ready to respond to the request, it interrupts itself and performs the service.
When set Disable, activity will neither prevent the system from going into a power management mode nor awaken it.
1.IRQ1 (Keyboard)
2.IRQ3 (COM 2 )
3.IRQ4 (COM 1)
4.IRQ5 (LPT 2)
5.IRQ6 (Floppy Disk)
6.IRQ7 (LPT 1)
7.IRQ8 (RTC Alarm)
8.IRQ9 (IRQ2 Redir)
9.IRQ10 (Reserved)
10.IRQ11 (Reserved)
11.IRQ12 (Reserved)
12.IRQ13 (Coprocessor)
13.IRQ14 (Hard Disk)
14.IRQ15 (Reserved)
Award BIOS 4.5 Setup UtilityChipset Features Setup § Page 1
Award Software
PCI Configuration Setup
This section describes configuring the PCI bus system. PCI, or Personal Computer Interconnect, is a system which allows I/O devices to operate at speeds nearing the speed the CPU itself uses when communicating with its own special components. This section covers some very technical items and it is strongly recommended that only experienced users should make any changes to the default settings.
PCI Slot Configuration
Slot x Using INT#
Some PCI devices use interrupts to signal that they need to use the PCI bus. Some devices, notably most graphics adapters, may not need an interrupt service at all. Each PCI slot is capable of activating up to four interrupts, INT# A, INT# B, INT# C and INT# D. By default, a PCI slot is allowed INT# A. Assigning INT# B has no meaning unless the device in the slot requires two interrupt services rather than just one. Likewise, using INT# C can only mean the device requires three interrupts and similarily for INT# D.
Selecting the default, AUTO, allows the PCI controller to automatically allocate the interrupts.
1st/2nd/3rd/4th Available IRQ
A INT# is an interrupt request which is signaled to and handled by the PCI bus. However, since the operating system usually has the final responsibility for handling I/O, INT#s can be mapped to an IRQ if the device occupying a given slot requires an IRQ service. By default, IRQ’s 9 and 10 to PCI are mapped to PCI devices, but any available, unused IRQ can be used.
You can select which INT# is associated with each PCI slot and which conventional IRQ is associated with one of the two available INT#s. The IRQ settings must be the same as the jumper settings on the motherboard.
A setting of NA means the IRQ has been assigned to the ISA bus and is not available to any PCI slot.
PCI IRQ Activated by
This sets the method by which the PCI bus recognizes that an IRQ service is being requested by a device. Under all circumstances, you should retain the default configuration unless advised otherwise by your system’s manufacturer.
Choices are Level (default) and Edge.
PCI IDE IRQ Map to
This allows you to configure your system to the type of IDE disk controller in use. By default, Setup assumes that your controller is an ISA (Industry Standard Architecture) device rather than a PCI controller. The more apparent difference is the type of slot being used.