Prob. / Score
1 / /25
2&3 / /35
4 / /20
5 / /25
6 / /35
Total

EECS140 Final

Name______

SID______

1)In the gain-boosting circuit below, assume that the opamp has infinite input impedance, zero output impedance, and a gain A(s) = A0/(1+s/p). Assume that both MOSFETs remain in saturation. Assume that the current source load has an impedance RL.

a)Draw the low frequency small signal model of the circuit (replacing the opamp with the expression Vo=A(s)(V+-V-), and noting that VREF is a small-signal ground )

b)What is the low frequency impedance Rout seen at the drain of M2 assuming RL is infinite?

c)What is the low frequency impedance Rin seen at the source of M2 assuming RL is very large but finite?

d)Ignoring all capacitors other than CL, and assuming RL is inifinite, what are the complex impedances Zd and Zout? (hint: Zd should have a pole and a zero)


2) Your friend has designed a two stage Miller-compensated CMOS op-amp. She has already added a compensation capacitor Cc that works for her application. The compensated op-amp has a low frequency pole at 1Mrad/sec, a low frequency gain of 1000, and a second pole at 100Mrad/sec. There are several other poles at frequencies around 3Grad/sec.

  1. (10) Draw a Bode plot (magnitude and phase) of the compensated open-loop amplifier
  1. (5) Is this amplifier stable in unity gain feedback? If yes, estimate the phase margin. If not, why not?
  1. (5) Is this amplifier stable with a feedback factor of 0.1 (gain of 10)? If yes, estimate the phase margin. If not, why not?
  1. (5) If you want to use the amplifier in unity gain feedback with a phase margin of at least 45 degrees, which capacitor would you change (C1, C2, or Cc), which pole(s) would that move, and how much would you need to move it/them?

3) (10) If you had a telescopic cascode amplifier with the same open loop poles and gain as described above, and you wanted a phase margin of 45 degrees in unity gain feedback, where would you add capacitance to achieve it, what pole(s) would you move, and how much would you need to move it/them? What would your new unity gain frequency be?

4) For the circuit on the left, express each answer in terms of L, Rs, and C.

a)Write down the expression for ωo.

b)Find the quality factor at ωo, Q = |Im(Zin(ωo))|/|Re(Zin(ωo))|.

c)What is |Zin(ωo)|?

For the circuit on the right, ignore the transistor capacitance.

d)Write an expression for loop gain |Aloop| terms of gm and Zin.

e)Find the gm required for oscillation (i.e. |Aloop| > 1).

f)What is the minimum current Itail required for oscillation? Express in terms of Zin, µn, Cox, and W/L.

5) Given the supply-independent bias circuit below,

a)design a startup circuit to prevent zero-current startup. Show W/Ls for all transistors.

b)Assume Vdsat1 is approximately 600mV, and the magnitude of Vdsat3 is approximately 300mV. Design voltage references for NMOS transistors with Vdsatn = Vdsat1 / 2 and for PMOS transistors with |Vdsatp| = 2* |Vdsat3| . Show W/Ls for all transistors, possibly referring to (W/L)1, (W/L)3 etc.

6) In the switched-capacitor feedback circuit below, assume that C1/C2 = 10 and that the amplifier operates from +/-5V supplies.

a)What is the minimum low frequency gain of the opamp to ensure a closed-loop gain accuracy of 0.1%? (you may ignore charge injection and output offset)

b)If the opamp has an output of 4V with both inputs grounded, and you need less than 1mV of output error overall, what is the minimum low frequency gain op the opamp? (you may ignore charge injection)

c)If the charge injected by switch S1 turning off is 3fC, which capacitor must accommodate that charge, and what is its minimum value to ensure an output voltage error of less than 1mV?

d)If the amplifier has negligible input capacitance and an open-loop unity gain frequency of 109 rad/sec, what is the settling time constant  in feedback, and the minimum time for phi2 to be high to ensure settling to within 0.1% accuracy? (you may ignore slew rate)

e)If C2 is 10pF, and the amplifier has a maximum slewing current of 10mA, what is the slew rate, and the time required for the amplifier output to slew 5V?


Prob 6 cont. f) Fill in the traces for VA, VB, and Vo. Assume zero charge injection and no output offset. Assume that the period of phi1 and phi2 has been chosen to just allow 0.1% settling, and no slew rate limitations. Clearly label your voltages!!!