EEEE 482 — Electronics II

Lab #0: Common-Emitter Amplifier Design

Overview

The objective of this lab is to design, simulate, and verify the performance of a common-emitter amplifier.

Background

A common-emitter amplifier is a widely used voltage amplifier due to its high gain and its reasonable tolerance to variations in transistor parameters. A discrete design for the common-emitter amplifier is shown in Figure 1. Assuming that the base current is small compared to the current in R1 and R2 we treat R1 and R2 as a voltage divider that sets the voltage at the base of the transistor. If Beta is high then IC and IE are approximately equal to the voltage at the base minus 0.7 volts divided by (Re1 + Re2), which is not dependent on Beta.

Figure 1. Common-Emitter Amplifier Schematic

Pre-Lab

Review the planned experiment and record relevant background information and equations that will be used for design of the common emitter amplifier (such as 2N3904 datasheet, equations for small signal voltage gain, etc.). Design and simulate the amplifier to meet the design specifications you pick.

Each student will randomly pick design specifications:

(1) a minimum value for magnitude of voltage gain: 20 22 24 26 28 30 [V/V] ( 10%); (note that the actual gain is negative in a common-emitter amplifier — i.e., –20 V/V, etc.);

(2) a power supply voltage value: 14 15 16 [V].

The required minimum output swing specification (peak-to-peak amplitude) is 5 V less than your supply voltage. For example, if your supply voltage is 14 V, your output voltage must be able to swing 4.5 V, for a total peak-to-peak output swing of 14 – 5 = 9 V.

Each student will design the amplifier by selection of R1, R2, RC, Re1 and Re2 using standard 10% tolerance resistor values (no parallel/series resistor combinations are allowed). Use 100μF capacitors for C1-C3. The 2N3904 npnBJTSPICE model can be found by searching for the Q2N3904 part. Load resistance is constant at 10 k.

Design approach(you will need to refine (use standard resistor values) to get to your final design, but this can provide a starting point):

  1. Assume Beta is 150, VBE is 0.7 V and IC for the 2N3904 npn Transistor is 6.0mA, RL=10K ohms.
  2. Pick the supply voltage, VCC, and the desired voltage gain Av
  3. Set RC to meet the output voltage swing specification (remember to consider both VCC supply and transistor saturation).
  4. Choose 0.15*VCCVB0.35*VCC.
  5. Set I1=10*IB Calculate R1
  6. Set I2=9*IB Calculate R2
  7. Set (Re1 + Re2) to get IC= 6mA.
  8. Use the small-signal gain specification to determine Re1. Note that the small-signal voltage gain includes the effect of RL.
  9. Round calculated resistor values to standard 10% tolerance, then analyze the resulting design to verify that it meets the design specifications.
  10. Verify your hand calculations using SPICE.

Lab Exercise

Build the circuit of Figure 1 using your designed resistor values. Use a signal frequency of 10 kHz, and initialamplitude of 100 mV to measure your voltage gain. You will likely need to increase the amplitude of the input signal in order to confirm that you can accommodate the required amount of voltage swing at the output. For example, if you had a target peak-to-peak swing of 9 V at the output and a measured voltage gain magnitude of 30 V/V, you would need an input signal of 9/30 V = 300 mV peak-to-peak, or 150mV amplitude, in order to drive the output with the target amount of swing.

  • Summarize your design calculations, as well as the re-analysis of your design after rounding calculated resistor values to standard 10% tolerance values. (see Below).
  • Compare hardware results to simulated results. Discuss any discrepancies.


Appendix: Monte Carlo Analysis (Orcad 9.2 Lite Edition)

Background

Monte Carlo analysis allows us to evaluate the impact of component tolerances and other non-idealities on circuit performance. Following are instructions on how to perform a successful Monte Carlo simulation.

  1. Adding Tolerances to Resistors
  2. Double-click the resistor symbol to which you wish to add tolerance.
  3. In the “Filter by” pull-down menu select “Orcad-Pspice”.
  4. At the far right end of the table, under the tolerance label, enter the desired tolerance value in percentage format (i.e., 10%).
  5. Click “Apply” in the upper left-hand corner to activate the value entered.
  6. Close the properties window.
  7. Setup Simulation Profile
  8. For a new simulation:
  9. Hit “New Simulation Profile” icon, .
  10. Input a profile, leave the “Inherited from” empty.
  11. Follow “For existing profile” steps from here on.
  12. For existing profile:
  13. Hit “Edit Simulation Settings” icon, .
  14. Simulation Settings window will pop up.
  15. Choose “Time domain (transient)” under Analysis type.
  16. Input proper time interval for “Run to time” (i.e., about 1 period).
  17. Select “Monte Carlo/Worst Case” in Options.
  18. Type in the name for “Output variable” (i.e., V(RL:2)).
  19. Input “Number of runs” (usually given).
  20. Type any number between 1 and 32767 into the “Random number seed” box.
  21. Click “More Settings” button on the lower right-hand corner.
  22. Choose “the maximum value (MAX)” from the pull-down menu.
  23. Click Apply.
  24. Hit OK, then OK again.

(cont’d)

  1. Running Capture CIS
  2. Hit the blue “Run Pspice” button on the tool bar . [Pspice window will pop up and simulation should be running at this time]
  3. Hit OK to close the window that pops up.
  4. The graph will then pop up with the voltage you wanted, provided you placed a voltage probe in the circuit.
  5. If it’s blank it is because you did not place a probe in the circuit. You can do so at this time and the corresponding voltage curve should appear immediately on the graph.
  6. How to Get a Performance Analysis Layout (Histogram)
  7. In the top menu, click on “Trace” and then “Performance Analysis”.
  8. In the window that pops up, click on the “Wizard” button at the bottom.
  9. Click NEXT.
  10. Select “Max” from the list and click NEXT.
  11. In the text box, type in the same thing you put in the “Output Variable” for the Monte Carlo profile (i.e., V(RL:2)).

Click FINISH and you should see the performance analysis above the graph.

Electronics II – EEEE 482 — Lab #0: Common-Emitter Amplifier Design — Rev 2015_1 Page 1

Rochester Institute of TechnologyDr. Lynn Fuller, et.al.