Consider the Following Circuit

HW4 LNA design

As I repeatedly said in class, your HW4 is to design an LNA. Architecture selection, schematic design, device sizing, schematic simulation, and performance comparison are required. Layout is not required. You can either a) select a recent paper that you liked and try to reproduce similar results to what they have but in your available process; or b) use the following architecture and perform your own design and simulation. In either case, you could follow the design steps that we went through in class. Your main performance goal will be noise figure and linearity (IIP3), but you should limit your power to “reasonable levels”. Since you may be using different processes and design for different frequencies, no specific noise figure or IIP3 numbers will be given. Grading will be based on 1) demonstrated understanding of the issues and compromises and 2) your included comparison to similar LNAs. Make sure you state the resulting noise figure (at wo), Ibias, transistor widths, component values, and gain (at wo) for the amplifier.

You can assume Ls to have infinite Q, but inductors Lg and Ld have associated resistances due to their finite Q (i.e., the values of Rpg and Rpd are set by the Q and inductance value of Lg and Ld, respectively). If you assume off-chip inductor, you can use Q = 50; if you assume on-chip inductor, take Q=5. You can use RF frequency wo = (2π)1.8 GHz or a different number of your choice. Cbig should be sized large enough to be viewed as short. You can ignore the noise contribution of the bias and cascade circuit. You can take c = j0.55, γ =3, δ =6, if your process does not provide these numbers. You can compare your noise figures when you take c=0 or j1.

If you want to increase your overall voltage gain, you may want to use a second stage. But if Vout in the above figure is going to the transducer input of the mixer, you can achieve reasonable gain by sizing Ld appropriately without a second stage.

If you want to try a differential LNA, you can use the architecture given in the notes.

HW 5 Mixer design

You are to design and simulate an active CMOS mixer. You can either implement a single balanced mixer if you did a single ended LNA in HW4, or a double balanced mixer (Gilbert cell) if you had a differential LNA from HW4. In either case, you could implement your architecture with or without input impedance matching. However, if you are planning to join the LNA and mixer together (which is what I would recommend), you don’t want to have 50 ohm input impedance matching on your mixer. In this case, your LNA output load will be the input capacitance of the mixer. In any case, you can assume that the IF frequency is low or you have direct conversion so that you don’t need any output transformer or impedance matching network.

Again, only schematic simulation is required. No need for layout. For inductors, use ideal inductor/series-resistor combinations with appropriate resistance values determined by a suitable Q. In testing your stand alone mixer, you can use ideal voltage sources as your RF input and LO signal.

Report, by simulation and/or analysis, schematic implemented, sizes or all devices, noise figure, linearity, conversion gain, power, output signal swing limit, port isolation, and anything else that you think deserves mentioning.

We will look at one student’s design in class.

HW6 VCO design

You are to design a voltage controlled oscillator, later to be used in a phase locked loop to generate LO signals for your mixer down converter.

You can choose either a ring oscillator or a cross coupled LC oscillator architecture. In class, I recommended implementing a ring oscillator with either a single-ended inverter or a Maneatis cell as your delay cell, for single-ended or fully differential ring oscillator respectively. You can use limiting amplifiers to convert the VCO output into a square wave signal if it is not already in square wave form.

Again, only schematic simulation is required. No layout needed. If you need an inductor in your LC oscillator, use an ideal inductor in series with a resistor whose value is appropriately determined by a suitable Q. For the Maneatis ring oscillator, you should include the appropriate biasing circuit.

Report, by simulation and/or analysis, schematic implemented, sizes or all devices, VCO frequency tuning range and the frequency vs control voltage curve, VCO output waveform at three oscillation frequencies, phase noise spectrum at three oscillation frequencies, VCO power consumption and how it varies with frequency, and anything else that you think deserves mentioning.