Nano-Technology based Metrology Needs : Ideas from the Semiconductor Industry

Alain C. Diebold, International SEMATECH, Austin, TX 78741

In 2004, the integrated circuit (IC) already contains millions of devices that can be classified as nanotechnology. The feature dimensions of transistors in microprocessors have gate lengths less than 40 nm and the International Technology Roadmap for Semiconductors (1) predicts gate lengths of less than 10 nm by 2015. The dimensions of gate dielectric layers in todays transistors are less than 2 nm in thickness, and on-chip interconnect wires and the vias that connect layers of these metal wires have barrier layers close to these dimensions. The interfacial layers between these thin films are engineered during the fabrication of these transistors. Successful manufacturing of IC s requires metrology that controls the multi-million transistors on each chip. Defects that serve as yield killers have similar dimensions to the features themselves. It is important to note that the manufacturing processes and equipment that will be used three years from now in the 65 nm IC technology node (w/microprocessors having 25 nm transistor gate lengths) are already being tested by IC manufacturers. The progression of alpha tool to beta tool to final tool takes one year for each step. Thus the physical and electrical measurement technology for this technology node is also being tested. The development and manufacture of these nano-IC’s requires materials characterization and metrology develop ahead of the process tool development if we are going to be ready for measurement needs 10 years of more in the future. A critical aspect of this development is that availability of features fabricated from the materials that will be used in the future.

A key concept for manufacturing process control that is often missed is the need to rapidly collect statistically significant data. Today, we often measure one value from a local distribution of values (one site on a wafer) or an average value for that local distribution. Ideally, we would measure the average and width of the local distribution in way that reflects the variation across the chip. Then the measurement of across the wafer and wafer - to - wafer variation becomes a matter of sampling strategy. Inherent in this discussion is the growing concern that test structures do not reflect actual on chip variation. Another implicit concept is that measurement on patterned structures is critical. So called “Out of the Box” ideas such as measuring critical dimensions (e.g., transistor gate length) using a method that never actually images the individual features must be considered. The example here is work of Ausschnitt. (2) Instead of measuring the width of individual lines, the average length of an array of lines and spaces is measured. This information is then used to control the focus and exposure of the lithographic patterning step. The final result is control of the critical dimension of line width. The ability to control average transistor linewidth and reduce the range of values will become more important as well as more difficult.

Optical and Electrical measurement methods have a long history of moving from lab to the FAB (IC factory). Interface sensitive methods such as optical second harmonic generation have been underutilized. Thanks to the availability of new laser technology, ultra-fast optical methods can be applied to the materials of the future. Faraday measurements can be applied to spin transport in spintronics. X-ray reflectivity provides the ability to measure and control buried interfaces in opaque materials. It application to patterned features and future materials stacks requires much closer ties between the laboratory systems and the clean room compatible systems that use optics capable of rapid measurement. Once again the need to couple metrology research and development to the materials set needs to be a mandatory aspect of every project. Although the devices of the future are predicted to be rather similar to those used in today’s IC, the use of new substrate materials such as silicon on insulator, strained silicon on insulator, or germanium on insulator greatly impact the measurement itself. New transistor device structures such as the so-called FINFET may change the orientation of the film thickness measurement from horizontal to vertical.(3)

It is important to note that the ITRS already contains section on emerging device technology and the integration of high frequency communications capability. There are real metrology needs in each area.(1)

In addition to the individual process measurements, the need for development of new microscopy should not be overlooked. Although microscopes are specialized to meet the needs of specific applications such as line width (critical dimension) measurement. The link between the developments of advanced transmission electron microscopy (TEM) and its subsequent impact on scanning electron microscopy (SEM) deserve mention. Aberration correction lens for TEM are moving into some applications of SEM. High voltage SEM is being considered as a potential method for future linewidth measurements. The point projection microscope (electron holography) remains a potential microscope for applications beyond the 10 year horizon. The big advantage is the ability to measure average linewidth and the width of the distribution of linewidths. The impact of TEM and TEM microanalysis on materials and process development will continue to make it s key method for all nanotechnology. Thus the TEAM (Transmission Electron Aberration – Corrected Microscope) project is a fundamental requirement for future metrology. The ultimate view of all materials would be an atom by atom map of a nanostructure. The Local Electrode Atom Probe (LEAP) is being developed an requires an infrastructure of national lab and university experts for method improvement and applications development.

The brief nature of this abstract does not allow one to cover all metrology research and development, even at a high level. A review of the metrology needs for the IC industry including a look at those required for nano-technechnology is available in the proceedings of the NIST sponsored conference Characterization and Metrology for ULSI Technology.(3) This review is based on the semiconductor industry’s ITRS Metrology Roadmap.

References

  1. See the Metrology Roadmap in the International Technology Roadmap for Semiconductors published by the Semiconductor Industry Association.
  2. C.P. Ausschnitt, et. al., Process Window Metrology, In Metrology, Inspection, and Process Control for Microlithography XIV, Neil T. Sullivan Ed., SPIE Vol. 3998, 2000, pp 158- 166.
  3. A.C. Diebold, The Requirements and Limits of Metrology Technology, Proceedings of the 2003 International conference on Characterization and Metrology for ULSI Technology, AIP, New York, pp 81-96.