-- Test Bench Shift Register
-- Marc Mackey
------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_textio.all;
use STD.textio.all;
use IEEE.std_logic_unsigned.all;
entity shiftregister_test is
end shiftregister_test;
architecture test of shiftregister_test is
component shift_register
port (
SI : in std_logic;
SO : out std_logic;
Rst : in std_logic;
En : in std_logic;
clk : in std_logic;
Dout : out std_logic_vector(1023 downto 0);
reg_preamble : out std_logic_vector(4 downto 0);
reg_syncword : out std_logic_vector(63 downto 0);
reg_trailer : out std_logic_vector(3 downto 0);
reg_AM_ADDR : out std_logic_vector(2 downto 0);
reg_type : out std_logic_vector(3 downto 0);
reg_flow : out std_logic;
reg_arqn : out std_logic;
reg_seqn : out std_logic;
reg_HEC : out std_logic_vector(7 downto 0);
reg_parity : out std_logic_vector(33 downto 0);
reg_LAP : out std_logic_vector(23 downto 0);
reg_SR : out std_logic_vector(1 downto 0);
reg_SP : out std_logic_vector(1 downto 0);
reg_UAP : out std_logic_vector(7 downto 0);
reg_NAP : out std_logic_vector(15 downto 0);
reg_Class : out std_logic_vector(23 downto 0);
reg_AM_ADDR2 : out std_logic_vector(2 downto 0);
reg_Clk : out std_logic_vector(25 downto 0);
reg_PageScan :out std_logic_vector(2 downto 0);
reg_payload_cha : out std_logic_vector(19 downto 0);
reg_payload_flow : out std_logic;
reg_payload_length : out std_logic_vector(4 downto 0);
reg_payload_DM1body : out std_logic_vector(135 downto 0);
reg_payload_CRC : out std_logic_vector(15 downto 0);
reg_payload_DH1body : out std_logic_vector(223 downto 0));
end component;
for s1 : shift_register use entity work.shift_register(RTL);
signal SI : std_logic;
signal SO : std_logic;
signal Rst : std_logic;
signal En : std_logic;
signal clock : std_logic;
signal Dout : std_logic_vector(1023 downto 0);
signal reg_preamble : std_logic_vector(4 downto 0);
signal reg_syncword : std_logic_vector(63 downto 0);
signal reg_trailer : std_logic_vector(3 downto 0);
signal reg_AM_ADDR : std_logic_vector(2 downto 0);
signal reg_type : std_logic_vector(3 downto 0);
signal reg_flow : std_logic;
signal reg_arqn : std_logic;
signal reg_seqn : std_logic;
signal reg_HEC : std_logic_vector(7 downto 0);
signal reg_parity : std_logic_vector(33 downto 0);
signal reg_LAP : std_logic_vector(23 downto 0);
signal reg_SR : std_logic_vector(1 downto 0);
signal reg_SP : std_logic_vector(1 downto 0);
signal reg_UAP : std_logic_vector(7 downto 0);
signal reg_NAP : std_logic_vector(15 downto 0);
signal reg_Class : std_logic_vector(23 downto 0);
signal reg_AM_ADDR2 : std_logic_vector(2 downto 0);
signal reg_Clk : std_logic_vector(25 downto 0);
signal reg_PageScan : std_logic_vector(2 downto 0);
signal reg_payload_cha : std_logic_vector(19 downto 0);
signal reg_payload_flow : std_logic;
signal reg_payload_length : std_logic_vector(4 downto 0);
signal reg_payload_DM1body : std_logic_vector(135 downto 0);
signal reg_payload_CRC : std_logic_vector(15 downto 0);
signal reg_payload_DH1body : std_logic_vector(223 downto 0);
begin
s1 : shift_register port map (SI,SO,Rst,En,clock,Dout,reg_preamble,reg_syncword,reg_trailer,reg_AM_ADDR,reg_type,reg_flow,reg_arqn,reg_seqn,reg_HEC,reg_parity,reg_LAP,reg_SR,reg_SP,reg_UAP,reg_NAP,reg_Class,reg_AM_ADDR2,reg_Clk,reg_PageScan,reg_payload_cha,reg_payload_flow,reg_payload_length,reg_payload_DM1body,reg_payload_CRC,reg_payload_DH1body);
clk : process
begin
clock <='0','1' after 5 ns;
wait for 10 ns;
end process clk;
io_process : process
file infile : text is in "shift_register_temp.txt";
file outfile : text is out "shift_register_out.txt";
variable SI1,Rst1,En1 : std_logic;
variable SO1 : std_logic;
variable Dout1 : std_logic_vector(1023 downto 0);
variable buf : line;
variable reg_preamble1 : std_logic_vector(4 downto 0);
variable reg_syncword1 : std_logic_vector(63 downto 0);
variable reg_trailer1 : std_logic_vector(3 downto 0);
variable Dout2 : std_logic_vector(63 downto 0);
variable Dout3 : std_logic_vector(63 downto 0);
variable Dout4 : std_logic_vector(63 downto 0);
variable Dout5 : std_logic_vector(63 downto 0);
variable Dout6 : std_logic_vector(63 downto 0);
variable reg_AM_ADDR1 : std_logic_vector(2 downto 0);
variable reg_type1 : std_logic_vector(3 downto 0);
variable reg_flow1 : std_logic;
variable reg_arqn1 : std_logic;
variable reg_seqn1 : std_logic;
variable reg_HEC1 : std_logic_vector(7 downto 0);
variable reg_parity1 : std_logic_vector(33 downto 0);
variable reg_LAP1 : std_logic_vector (23 downto 0);
variable reg_SR1 : std_logic_vector (1 downto 0);
variable reg_SP1 : std_logic_vector (1 downto 0);
variable reg_UAP1 : std_logic_vector (7 downto 0);
variable reg_NAP1 : std_logic_vector (15 downto 0);
variable reg_Class1 : std_logic_vector (23 downto 0);
variable reg_AM_ADDR21 : std_logic_vector (2 downto 0);
variable reg_Clk1 : std_logic_vector (25 downto 0);
variable reg_PageScan1 : std_logic_vector (2 downto 0);
variable reg_payloadheader1 : std_logic_vector(7 downto 0);
variable reg_payload_cha1 : std_logic_vector(19 downto 0);
variable reg_payload_flow1 : std_logic;
variable reg_payload_length1 : std_logic_vector(4 downto 0);
variable reg_payload_DM1body1 : std_logic_vector(135 downto 0);
variable reg_payload_CRC1 : std_logic_vector(15 downto 0);
variable reg_payload_DH1body1 : std_logic_vector(223 downto 0);
variable my_line : LINE;
begin
while not(endfile(infile))loop
readline(infile,buf);
read(buf,SI1);
SI <= SI1;
read(buf,Rst1);
Rst <= Rst1;
read(buf,En1);
En <= En1;
wait until rising_edge(clock);
wait for 1 ns;
--SO1 := SO;
--write(buf,SO1);
--writeline(outfile,buf);
Dout1 := Dout(1023 downto 0);
write(my_line,string'("Data is"));
writeline(outfile,my_line);
write(buf,Dout1);
writeline(outfile,buf);
write(my_line,string'(""));
writeline(outfile,my_line);
------
reg_preamble1 := reg_preamble;
write(my_line,string'("Preamble is"));
writeline(outfile,my_line);
write(buf,reg_preamble1);
writeline(outfile,buf);
write(my_line,string'(""));
writeline(outfile,my_line);
------
reg_syncword1 := reg_syncword;
write(my_line,string'("Sync Word is"));
writeline(outfile,my_line);
write(buf,reg_syncword1);
writeline(outfile,buf);
write(my_line,string'(""));
writeline(outfile,my_line);
------
reg_trailer1 := reg_trailer;
write(my_line,string'("Trailer is"));
writeline(outfile,my_line);
write(buf,reg_trailer1);
writeline(outfile,buf);
write(my_line,string'(""));
writeline(outfile,my_line);
------
reg_AM_ADDR1 := reg_AM_ADDR;
write(my_line,string'("AM_ADDR is"));
writeline(outfile,my_line);
write(buf,reg_AM_ADDR1);
writeline(outfile,buf);
write(my_line,string'(""));
writeline(outfile,my_line);
------
reg_type1 := reg_type;
write(my_line,string'("Type is"));
writeline(outfile,my_line);
write(buf,reg_type1);
writeline(outfile,buf);
write(my_line,string'(""));
writeline(outfile,my_line);
------
reg_flow1 := reg_flow;
write(my_line,string'("Flow is"));
writeline(outfile,my_line);
write(buf,reg_flow1);
writeline(outfile,buf);
write(my_line,string'(""));
writeline(outfile,my_line);
------
reg_arqn1 := reg_arqn;
write(my_line,string'("ARQN is"));
writeline(outfile,my_line);
write(buf,reg_arqn1);
writeline(outfile,buf);
write(my_line,string'(""));
writeline(outfile,my_line);
------
reg_seqn1 := reg_seqn;
write(my_line,string'("SEQN is"));
writeline(outfile,my_line);
write(buf,reg_seqn1);
writeline(outfile,buf);
write(my_line,string'(""));
writeline(outfile,my_line);
------
reg_HEC1 := reg_HEC;
write(my_line,string'("HEC is"));
writeline(outfile,my_line);
write(buf,reg_HEC1);
writeline(outfile,buf);
write(my_line,string'(""));
writeline(outfile,my_line);
------
reg_parity1 := reg_parity;
write(my_line,string'("Parity is"));
writeline(outfile,my_line);
write(buf,reg_parity1);
writeline(outfile,buf);
write(my_line,string'(""));
writeline(outfile,my_line);
------
reg_LAP1 := reg_LAP;
write(my_line,string'("LAP is"));
writeline(outfile,my_line);
write(buf,reg_LAP1);
writeline(outfile,buf);
write(my_line,string'(""));
writeline(outfile,my_line);
------
reg_SR1 := reg_SR;
write(my_line,string'("SR is"));
writeline(outfile,my_line);
write(buf,reg_SR1);
writeline(outfile,buf);
write(my_line,string'(""));
writeline(outfile,my_line);
------
reg_SP1 := reg_SP;
write(my_line,string'("SP is"));
writeline(outfile,my_line);
write(buf,reg_SP1);
writeline(outfile,buf);
write(my_line,string'(""));
writeline(outfile,my_line);
------
reg_UAP1 := reg_UAP;
write(my_line,string'("UAP is"));
writeline(outfile,my_line);
write(buf,reg_UAP1);
writeline(outfile,buf);
write(my_line,string'(""));
writeline(outfile,my_line);
------
reg_NAP1 := reg_NAP;
write(my_line,string'("NAP is"));
writeline(outfile,my_line);
write(buf,reg_NAP1);
writeline(outfile,buf);
write(my_line,string'(""));
writeline(outfile,my_line);
------
reg_Class1 := reg_Class;
write(my_line,string'("Class is"));
writeline(outfile,my_line);
write(buf,reg_Class1);
writeline(outfile,buf);
write(my_line,string'(""));
writeline(outfile,my_line);
------
reg_AM_ADDR21 := reg_AM_ADDR2;
write(my_line,string'("AM_ADDR is"));
writeline(outfile,my_line);
write(buf,reg_AM_ADDR21);
writeline(outfile,buf);
write(my_line,string'(""));
writeline(outfile,my_line);
------
reg_Clk1 := reg_Clk;
write(my_line,string'("Clk is"));
writeline(outfile,my_line);
write(buf,reg_Clk1);
writeline(outfile,buf);
write(my_line,string'(""));
writeline(outfile,my_line);
------
reg_PageScan1 := reg_PageScan;
write(my_line,string'("Page Scan is"));
writeline(outfile,my_line);
write(buf,reg_PageScan1);
writeline(outfile,buf);
write(my_line,string'(""));
writeline(outfile,my_line);
------
------DM1 packet header------
reg_payload_cha1 := reg_payload_cha;
write(my_line,string'("Payload Channel is"));
writeline(outfile,my_line);
write(buf,reg_payload_cha1);
writeline(outfile,buf);
write(my_line,string'(""));
writeline(outfile,my_line);
------
reg_payload_flow1 := reg_payload_flow;
write(my_line,string'("Payload Flow is"));
writeline(outfile,my_line);
write(buf,reg_payload_flow1);
writeline(outfile,buf);
write(my_line,string'(""));
writeline(outfile,my_line);
------
reg_payload_length1 := reg_payload_length;
write(my_line,string'("Payload Length is"));
writeline(outfile,my_line);
write(buf,reg_payload_length1);
writeline(outfile,buf);
write(my_line,string'(""));
writeline(outfile,my_line);
------
reg_payload_DM1body1 := reg_payload_DM1body;
write(my_line,string'("DM1 Payload Body is"));
writeline(outfile,my_line);
write(buf,reg_payload_DM1body1);
writeline(outfile,buf);
write(my_line,string'(""));
writeline(outfile,my_line);
------
reg_payload_CRC1 := reg_payload_CRC;
write(my_line,string'("Payload CRC is"));
writeline(outfile,my_line);
write(buf,reg_payload_CRC1);
writeline(outfile,buf);
write(my_line,string'(""));
writeline(outfile,my_line);
------
reg_payload_DH1body1 := reg_payload_DH1body;
write(my_line,string'("DH1 Payload Body is"));
writeline(outfile,my_line);
write(buf,reg_payload_DH1body1);
writeline(outfile,buf);
write(my_line,string'(""));
writeline(outfile,my_line);
------
end loop;
wait;
end process io_process;
end test;