Table of Contents:
1 List of Figures ii
2 List of Tables iii
3 List of Symbols iv
4 List of Definitions v
5 Introductory Materials 1
5.1 Abstract 1
5.2 Acknowledgement(s) 1
5.3 Problem Statement 1
5.4 Operating Environment 2
5.5 Intended user(s) and intended use(s) 2
5.6 Assumptions 2
5.7 Limitations 6
5.8 Expected end product and other deliverables 7
6 Approach and Product Design Results 8
6.1 Design Objectives 8
6.2 Functional Requirements 8
6.3 Design Constraints 8
6.4 Technical Approach Considerations and Results 8
6.5 Testing Approach Considerations 9
6.6 Recommendations for Project Continuation or Modification 9
6.7 Detailed Designs 9
6.8 Sutherland Design 10
6.9 Dautremont Design 17
6.10 Mousetrap Design 22
6.11 Design Selection Criteria 28
7 Resource Requirements 30
7.1 Personnel Effort Requirements 30
7.2 Resource Requirements 31
7.3 Estimated Financial Requirements 32
7.4 Schedule 33
8 Closure Materials 36
8.1 Team Information 36
8.2 Summary 37
8.3 References 37
1 List of Figures
Figure 1 Top View of Data Pipeline …………………………………………………. / 3Figure 2 Latches ……………………………………………………………………… / 4
Figure 3 Pre-Driver …………………………………………………………………... / 4
Figure 4 Pads/Pad Drivers ……………………………………………………………. / 5
Figure 5 Clock ………………………………………………………………………... / 5
Figure 6 Sutherland FIFO Diagram ……….…………………...…………………….. / 10
Figure 7 C-Muller Transistor Level Design….……………………………………….. / 12
Figure 8 Switch Transistor Level Design………………………………………….…. / 14
Figure 9 Inverter Transistor Level Design……………………………………………. / 15
Figure 10 FIFO Component Level Design…………………………………………... / 16
Figure 11 Simulation of Sutherland FIFO……………………………………………. / 17
Figure 12 Data must pass through all storage elements………………………………. / 18
Figure 13 Parallel architecture reduces number of elements data must pass through... / 18
Figure 14 Tokens are used to allow storage elements to read and write……………… / 19
Figure 15 Gates used in circuit……………………………………………………….. / 19
Figure 16 Control Logic Circuit………………………………………………………. / 20
Figure 17 Control logic and data storage……………………………………………... / 21
Figure 18 Dissimilar Token and Token Sense lines allow operations to occur. The
inverters shown are necessary for proper operation……………………….. / 21
Figure 19 Block Diagram of Mousetrap Pipeline…………………………………….. / 22
Figure 20 Schematic of the Data Latch……………………………………………….. / 23
Figure 21 Simulation Results for Test of Single Data latch………………………….. / 24
Figure 22 Schematic of Dual Rail Monotonic XOR/XNOR Gate……………………. / 25
Figure 23 Simulation Results for Test of Single XOR/XNOR Logic Gate…………... / 26
Figure 24 Schematic of Single Bit of Mousetrap Pipeline……………………………. / 27
Figure 25 Original Schedule………………………………………………………….. / 33
Figure 26 Updated Schedule………………………………………………………….. / 34
Figure 27 Original Deliverable Schedule…………………………………………….. / 35
Figure 28 Updated Deliverable Schedule…………………………………………….. / 35
2 List of Tables
Table 1 Gate Truth Tables……………………………………………………………. / 19Table 2 Original Personal Effort Requirements……………….……………………... / 30
Table 3 Revised Personal Effort Requirements………………………………………. / 30
Table 4 Original Resource Requirements…………………………………………….. / 31
Table 5 Revised Resource Requirements …………………..………………………... / 31
Table 6 Estimated Financial Requirements…………………………………………... / 32
Table 7 Revised Financial Requirements…………………………………………….. / 32
Table 8 Team Information …………………………………………………………… / 36
3 List of Symbols
Symbol / Meaning/ AND gate. The standard logic gate, as described in the Dautremont design.
/ Muller-C element. This symbol has one inverted input, as described in the Sutherland design.
/ NMOS transistor. Basic transistor symbol, referenced in the Dautremont and Sutherland designs.
/ NOT gate. The standard inverter, as described in the Sutherland and Dautremont designs.
/ PMOS transistor. Basic transistor symbol, referenced in Dautremont and Sutherland designs.
/ Switch. The appropriate input is chosen based on the control wire, and the input is inverted. This component is described in the Sutherland design.
/ Tristate inverter. The conventional tristate inverter, as described in the Dautremont design.
/ XOR gate. The standard XOR logic gate, as described in the Dautremont design.
4 List of Definitions
Asynchronous – Lacking a common signal to coordinate behavior, especially the electrical signals between two circuit components.
Cadence – Integrated circuit design tool that allows for front to back circuit design.
Circuit family – The specific architecture used to implement a component. It often determines overall speed and size.
DLL – Delay lock loop
DRC – Design rule check – Verifies the geometry of a circuit layout conforms to certain specifications so as to guarantee a high yield of good die.
FIFO – First in first out
Forward latency – Delay between data valid signal and the first QED clock edge.
FO4 delay - Delay time for the propagation of a signal through an inverter which feeds four other inverters.
HDL – Hardware description language
Integrated circuit – A tiny complex of electronic components and their connections that is produced in or on a small slice of material (as silicon).
IC – Integrated circuit
Lambda based design rules – Design rules based on a process-specific length lambda. All design rules are then specified as integral multiples of lambda. In this way, a given design becomes scalable and process independent.
Layout – A geometric layout of the physical layers of material in an integrated circuit.
LVS – Layout versus schematic – A process used in the Cadence technology suite to compare the schematic with an extracted form of the layout.
Maximum data throughput – The maximum amount of data that can be produced by the pipeline in a specified amount of time.
QED – Signal from the graphics processor requesting data from the pipeline.
Reverse latency – How quickly new data can be accepted when the pipeline is full.
Schematic – A drawing or diagram of the circuit that makes it easier for the user to visualize and understand in terms of mathematical equations.
Slew rate – The maximum rate of change of an output signal.
Specifications – a detailed, precise presentation of something or a plan or proposal for something.
Tapeout – Final layout draft - After the iterative process of fixing errors in the layout and running simulations, a layout will be created that meets all the rules of integrated circuit design and the specifications of the process.
Topology – A branch of mathematics concerned with those properties of geometric configurations (as point sets) that are unaltered by elastic deformations (as a stretching or a twisting)
Verilog – A hardware description language used to describe the behavior of a circuit and verify that a design is correct.
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5 Introductory Materials
This section of the design report will provide an overview of the read data path pipeline project. First, it will provide the motivation and problem statement that define the project. Next, it will explain the environment the circuit is being designed for, and who will use the circuit. Finally, it will outline assumptions and limitations inherent in the work, and describe generally what the final product should be.
5.1 Abstract
The graphics card in a computer is constantly refreshing the display by reading data from graphics memory. The time between data being ready in the graphics memory and the graphics processor being ready to handle the data is not constant due to process and operating variations. In order to ensure the data is passed from the memory to the processor at the right time, a pipeline will be implemented to control the flow of data. This pipeline will transfer data from the memory to the processor with the right timing to achieve the required throughput, independent of process variations and operating conditions. This will allow the graphics card to function correctly, since data is being read according to the asynchronous specification.
5.2 Acknowledgement(s)
Thanks to Brent Keeth and Brian Johnson from Micron Technology for creating a project that a student can handle in a Senior Design Project, and for being contact points within Micron.
Thanks to Dr. Randy Geiger for being the faculty advisor for the project, and for providing his knowledge and experience in the area of integrated circuit design.
Thanks to MOSIS for providing students the opportunity to fabricate a circuit. Without this help, the cost of fabrication would be out of reach for a senior design project.
5.3 Problem Statement
General problem statement: Micron Technology needs an integrated circuit for a graphics card that can quickly move data from graphics memory to a graphics processor. The data from the memory arrives at the processor asynchronously, so a data path pipeline is needed to mediate between the two timing configurations.
General solution approach: Use a data pipelining methodology to design an integrated circuit that can meet the timing specifications given by Micron. Using Cadence, develop the design into a schematic, verify the correctness of the design, lay out the design, and test the layout. Finally, fabricate the circuit and check functionality.
5.4 Operating Environment
The circuit will operate in a computer graphics card, which is a relatively stable environment. The temperature will be held between 0 and 80° C. There should not be any harsh weather conditions such as rain or wind since the chip will be part of a fully packaged integrated circuit.
5.5 Intended user(s) and intended use(s)
Knowing who will use this product and how it will be used is important to designing it correctly.
Intended Users:
· Micron Technology
· Electrical engineers who develop graphics cards
· Design engineers who will refine the design to work on smaller and faster fabrication processes
Intended Uses:
· Data buffer between the video driver and the system on which the graphics are displayed.
· Modular component for other devices that need a read pipeline in their data paths.
5.6 Assumptions
This section details the assumptions used in the design of the project. They provide important rationale for design decisions.
Updated Assumptions List:
1) A DLL will be provided to the read data path pipeline component.
The delay lock loop is a relatively complex component that is necessary to generate the QED signals in this project. Its design, however, is beyond the scope of this project. This work, then, is completed under the assumption that this functionality will be provided off chip.
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2) Power Source: 0 V to 3.3 V
This is a standard assumption for integrated circuits in a 0.6μ environment.
3) Four 32-bit registers will be sufficient for the FIFO.
This assumption allows the group to specify a total memory of 128 bits for the FIFO component, and helps minimize the area required for the component.
4) The design provided by the team will be scaled by Micron to meet their needs.
In this design, the team will use a lambda-based layout methodology and fabricate the circuit using a 0.5μ AMI process. Since Micron is interested in the design and its validity only, the assumption is that Micron will be responsible for modifying the design to meet their smaller process needs. This will include dealing with any problems involved in such a migration, such as increased parasitic capacitances and more pronounced leakage currents.
5) Corner model simulation will show range of latency
Because of process variations, the design must be able to meet certain absolute timing specifications dictated by the fast and slow corner latency. Fast and slow corners relate to changes in the clock as the delay lock loop attempts to align the signals.
6) The pipeline must fit the following block specifications.
Figure 1: Top View of Data Pipeline
This is the top view of the data pipeline showing how it will interact with the memory array, the clock, and the output driver.
Figure 2: Data Latches
Figure 2 shows how the data latches work with the QED signal, the pull-up/pull-down networks, and the clock. It also specifies the interface between the pipeline and the latches.
Figure 3: Pre-drivers
Figure 3 shows the pre-drivers that determine the slew rate of the pad driver by turning on a succession of parallel transistors in the driver.
Figure 4: Pads/Pad Drivers
The next step down the line is the pads/pad drivers shown in Figure 4. The pads/pad drivers make sure the circuit is being driven at the correct speed.
Figure 5: Clock
Figure 5 shows how the clock from the DLL breaks down to become the 4-phase clock that is sent to the read latches. The clock needs to be a 4-phase clock so that data is driven at double data rate.
5.7 Limitations
Limitations are factors that restrict the design or development of the product, and should be recorded to help in the design of the product.
Updated Limitations List:
1) To allow for complete testing of the fabricated circuit, it must be ready to send to MOSIS by January 12, 2004.
MOSIS fabrication of the circuit is supported by substantial grants from the National Science Foundation, without which, fabrication would be beyond the financial reach of this project. All chips fabricated by MOSIS, however, require a follow up report on chip performance. Submitting the chip design by this date offers the best possibility of getting the fabricated chip back before Spring semester ends, allowing chip testing.
2) The MOSIS student fabrication package has a limited pin count and chip size; therefore a special package will probably have to be purchased.
The standard fabrication package has 40 pins for input and output. Since the pipeline already has 32 pins for input, and 32 pins for output, clearly a larger package size will be required.
3) The area of the allowable design to be fabricated is 2.25 mm2.
MOSIS requires that the circuit sent for fabrication will be less than 1.5 mm x 1.5 mm which is a total area of 2.25 mm2. Therefore the design must meet these absolute area requirements.